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PDF LTC4255 Data sheet ( Hoja de datos )
| Número de pieza | LTC4255 | |
| Descripción | Quad Network Power Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC4255
Quad Network Power
Controller with I2C Compatible Interface
FEATURES
s Controls Four Independent –48V Power Channels
s Each Channel has Separate Relay Drivers, ON/OFF
Control, Short-Circuit Protection with Current
Foldback, Open-Circuit Detection, and Power Good
Indication
s Programmed via I2CTM Compatible Interface
s Five Bit Programmable Digital Address Allows
Control of up to 32 LTC4255s (128 Channels)
s Interrupt on FAULT Output can be used to Eliminate
Software Polling
s Programmable Current Limit and Open-Circuit
Duration Periods
s Programmable Latchoff or Autoretry after Short-
Circuit Faults
s Programmable Autoretry Duty Cycle
U
APPLICATIO S
s IP Phone Systems
s DTE Power Distribution
DESCRIPTIO
The LTC®4255 is a quad –48V network power controller
with independent relay drivers and I2C compatible inter-
face. Each channel can be turned on and off via software
control, while providing short-circuit protection, open-
circuit detection, and power good indication. The short-
circuit protection includes a current foldback feature to
reduce power dissipation in the switch during shorts and
start-up.
The serial interface allows up to 128 channels to be
controlled with only two digital lines. A FAULT output can
be used as an interrupt line to eliminate fault detection by
software polling.
External switches and current sense resistors allow easy
scaling of current and power dissipation levels and pro-
vide the maximum protection against voltage and current
spikes.
The LTC4255 is available in the 28-pin SSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
I2C is a trademark of Philips Electronics N.V.
TYPICAL APPLICATIO
12V
0.1µF
VCC
SCL
SDA
FAULT
AD0
AD1
AD2
AD3
AD4
LTC4255
RELAY1
RELAY2
RELAY3
RELAY4
DGND AGND VEE SENSE1 GATE1 OUT1 SENSE2 GATE2 OUT2 SENSE3 GATE3 OUT3 SENSE4 GATE4 OUT4
–48V
RS1
0.1µF 0.33Ω
100k
Q1 RS2
0.33Ω
Q1, Q2, Q3, Q4: FDC3612
RELAYS: V23079 SERIES
100k
Q2 RS3
0.33Ω
100k
Q3 RS4
0.33Ω
100k
Q4
4255 TA01
4255f
1
1 page  
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TYPICAL PERFOR A CE CHARACTERISTICS
LTC4255
IOUT vs VOUT
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–50 –40 –30 –20
VOUT (V)
TA = 25°C
VEE = –48V
–10 0
4255 G10
IGATE vs Temperature
65
GATE OFF
60 VGATE = VEE + 5V
55
50
45
40
35
–50 –25
0
25 50
TEMPERATURE (°C)
75 100
4255 G13
VEE Undervoltage Lockout
vs Temperature
–26
–27
–28
–29
–30
–31
–32
–50 –25 0
25 50
TEMPERATURE (°C)
75 100
4255 G16
IOUT vs Temperature
2.0
VOUT = VEE
1.8
1.6
1.4
1.2
1.0
0.8
–50 –25 0
25 50
TEMPERATURE (°C)
75 100
4255 G11
VGATE vs Temperature
13.6
13.4
13.2
13.0
12.8
12.6
12.4
12.2
–50 –25
0 25 50
TEMPERATURE (°C)
75 100
4255 G14
Relay Driver Output Low Voltage
(VOLR) vs Temperature
0.170
IRELAY = 50mA
0.165
0.160
0.155
0.150
0.145
0.140
0.135
0.130
–50 –25
0
25 50 75 100
TEMPERATURE (°C)
4255 G17
IGATE vs Temperature
–44
GATE ON
–46 VGATE = VEE
–48
–50
–52
–54
–56
–58
–50 –25
0 25 50
TEMPERATURE (°C)
75 100
4255 G12
ISENSE vs Temperature
–42
VSENSE = VEE
–43
–44
–45
–46
–47
–48
–50 –25 0
25 50
TEMPERATURE (°C)
75 100
4255 G15
AD0-4 Pullup Resistors to 5V (RPU)
vs Temperature
60
59
58
57
56
55
54
53
52
51
–50
0 50
TEMPERATURE (°C)
100
4255 G18
4255f
5
5 Page 
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LTC4255
APPLICATIO S I FOR ATIO
Normal Power-Up
Using channel 1 as an example, a normal power-up cycle
begins when the switch 1 enable bit (A0) and relay 1 enable
bit (A4) are set high and then latched into the chip by a
STOP bit on the serial interface (point A, Figure 9).
The RELAY1 output turns on immediately and energizes
an optional relay connecting the AGND and OUT1 pins to
the cable. After a fixed delay of approximately 18ms (tOD),
the GATE1 pin will start to pull high (point B). When the
threshold voltage of the FET is reached, current will begin
flowing in the external FET (point C). The voltage at the
OUT1 pin will then fall at a rate determined by the current
limit and the output load capacitance. Because the current
limit is lower when the OUT1 pin is near AGND due to the
foldback circuit, the voltage will fall slowly at first, then get
faster. At the same time, the current limit timer will start.
The OUT1 voltage must reach its final value and the analog
current limit circuit must turn off before the current limit
timer expires, or a current limit fault will be detected and
the FAULT pin will be pulled low.
When the voltage at OUT1 is within 2V of VEE, the Power_OK
(C0) bit will be set (point D) and the open-circuit enable
delay timer started. As long as the load current turns on
before the open-circuit enable delay timer expires, the
FAULT pin will remain in a high impedance state and the
current limit fault status bit (D0) and open-circuit fault
status bit (D4) bits will remain low, thus completing a
normal power-up sequence. The Power_OK bit will re-
main high until the switch is turned off by setting the
switch enable bit (AO) low or a short-circuit or open-
circuit condition turns off the switch.
A normal power-down sequence begins when the switch
enable bit (A0) and relay enable bit (A4) are cleared and
then latched into the chip by a STOP bit on the serial
interface (point E). The RELAY1 pin will go into a high
impedance state and the inductive voltage spike from the
primary coil will be clamped at about 18V. The relay will
typically disengage several milliseconds later. At the same
time, the GATE1 pin will be pulled low by a 50µA current
source, the FET will turn off, and the Power_OK bit will be
cleared.
SCL
SDA
SHORT-CIRCUIT STATUS
(D0)
OPEN-CIRCUIT STATUS
(D4)
POWER_OK
(C0)
FAULT
AO ACK
STOP BIT
RELAY1
GATE1
FET TURNS ON
AO ACK
OUT1
POWER OK
AB
tOD
C
D
E
Figure 9. Normal Power-Up and Power-Down Sequence on Channel 1
4255 F09
4255f
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LTC4255.PDF ] | |
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