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PDF LTC4245 Data sheet ( Hoja de datos )
| Número de pieza | LTC4245 | |
| Descripción | Multiple Supply Hot Swap Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
■ Allows Safe Insertion into Live CompactPCITM or
PCI ExpressTM Backplane
■ 8-Bit ADC Monitors Current and Voltage
■ I2CTM/SMBus Interface
■ dI/dt Controlled Soft Start
■ Simultaneous or Sequenced Turn-On
■ ±20V Absolute Maximum Rating for ±12V Supplies
■ No External Gate Capacitor Required
■ Dual-Level Circuit Breaker and Current Limit
■ Bus Precharge Output
■ Power Good Input with Timeout
■ Optional Latchoff or Autoretry After Faults
■ Alerts Host After Faults
■ Integrated LOCAL_PCI_RST# Logic
■ 36-Pin SSOP and 38-Pin (5mm × 7mm) QFN
Packages
U
APPLICATIO S
■ Live Board Insertion
■ CompactPCI, CompactPCI Express, CompactTCA,
PCI Express Systems
LTC4245
Multiple Supply Hot Swap
Controller with I2C
Compatible Monitoring
DESCRIPTIO
The LTC®4245 Hot SwapTM controller allows a board to
be safely inserted and removed from a live backplane in
multiple supply systems such as CompactPCI and PCI
Express. Using four external N-channel pass transistors,
the board supply voltages can be ramped up at an adjust-
able rate and in any desired sequence. An I2C interface and
onboard ADC allow monitoring of board current, voltage
and fault status for each supply.
The device features adjustable dI/dt controlled soft start
and foldback limited inrush current. A dual-level timed
circuit breaker and fast current limit protect each supply
against overcurrent faults. A power good input with timeout
allows a downstream supply monitor to disconnect the
board supplies. The device can be configured to function
without a –12V supply or with an extra 3.3V supply instead
of a 5V supply.
The controller has additional features to interrupt the host
when a fault has occurred, notify when output power is
good, detect insertion of a load card and power-up in
either the on or off state.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
CompactPCI Application
BACKPLANE CARD
CONNECTOR CONNECTOR
5VOUT
12VOUT
Sequenced Turn-On Waveform
BD_SEL#
10V/DIV
12VIN 12VSENSE 12VGATE 12VOUT 5VIN 5VSENSE 5VGATE
BD_SEL#
5VOUT
ON
HEALTHY#
SDA
SCL
ALERT#
PCI_RST#
LTC4245
PGI
LOCAL_PCI_RESET#
PRECHARGE
GND
3VOUT
VEEIN VEESENSE VEEGATE VEEOUT 3VIN 3VSENSE 3VGATE
SUPPLY
MONITOR
RESET
BOARD
RESET
TO BUS
–12VOUT
3.3VOUT
OUTPUT
VOLTAGE
5V/DIV
LOCAL_PCI_RST#
5V/DIV
12VOUT
5VOUT
3VOUT
VEEOUT
TIME (50ms/DIV)
4245 TA01b
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LTC4245
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. V12VIN = 12V, V5VIN = 5V, V3VIN = 3.3V, VVEEIN = –12V, unless otherwise noted.
SYMBOL
ADC
RES
VFS
INL
OE
FSE
TUE
tADC
Delays
tD
tPLH(GATE)
tPHL(GATE)
tPHL(UVL)
tCB
tACL
PARAMETER
Resolution (No Missing Codes)
Full-Scale Voltage (VFS = 255LSB)
12VIN, 12VOUT
12VIN – 12VSENSE, VEESENSE – VEEIN
5VIN, 5VOUT
5VIN – 5VSENSE, 3VIN – 3VSENSE
3VIN, 3VOUT
VEEIN, VEEOUT
GPIO
Integral Nonlinearity
Offset Error
Full-Scale Error
Total Unadjusted Error
Conversion Time
Turn-On Delay
Input High (ON) to Gates High Delay
Input High (BD_SEL#), Input Low (ON)
to Gates Low Propagation Delay
Supply Low to Gates Low Delay
Circuit Breaker Filter Delay Time
Active Current Limit Delay
tPHL(PGI)
tPHL(RST)
PGI Low to Gates Low
Output Low to LOCAL_PCI_RST# Low
tP(RST)
PCI_RST# to LOCAL_PCI_RST# Delay
I2C Interface Timing (Note 7)
fSCL(MAX)
tBUF(MIN)
tSU, STA(MIN)
tHD, STA(MIN)
tSU, STO(MIN)
Maximum SCL Clock Frequency
Min. Bus Free Time Between Stop/Start
Minimum Repeated Start Set-Up Time
Min. Hold Time After (Repeated) Start
Minimum Stop Condition Set-Up Time
CONDITIONS
(Note 7)
(Note 6)
VCFG = 0V, Open
VCFG = VCC
ΔVSENSE (Note 8)
Other 9 Channels
ΔVSENSE (Note 6)
VEEIN, VEEOUT
Other 7 Channels
All 13 Channels Once
ΔVSENSE, VEEIN, VEEOUT
Other 7 Channels
SS Open
CGATE = 1pF
12VIN, 5VIN, 3VIN, CGATE = 1pF
VEEIN, CVEEGATE = 1pF
ΔV12VSENSE = 300mV, C12VGATE = 10nF
ΔV5VSENSE = 150mV, C5VGATE = 10nF
ΔV3VSENSE = 150mV, C3VGATE = 10nF
ΔVVEESENSE = 300mV, CVEEGATE = 10nF
CGATE = 1pF
12VOUT, 5VOUT, 3VOUT, VPCI_RST# = 2V
VEEOUT, VPCI_RST# = 2V
Operates with fSCL ≤ fSCL(MAX)
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
MIN TYP MAX UNITS
8
13.744
62.47
5.5
3.75
31.24
3.75
–13.744
2.5
14.025
63.75
5.61
3.825
31.875
3.825
–14.025
2.55
14.306
65.03
5.72
3.9
32.51
3.9
–14.306
2.6
±0.5 ±2
±0.2 ±1.25
±0.5 ±1.5
±0.5 ±1.25
±0.3 ±1
±5
±5
665
70
35
Bits
V
mV
V
V
mV
V
V
V
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ms
ms
ms
60 100 150
15 30
0.3 1
2.1 3.5 4.9
3.3 5.5 7.7
16 22 28
0.9 2.3
0.85 2.1
0.7 1.8
25
12 20 28
9 15 21
10.2 17 23.8
60 200
ms
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
400
0.12 1.3
10 600
140 600
10 600
kHz
μs
ns
ns
ns
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LTC4245
PI FU CTIO S
PCI_RST#: Reset Input. Pulling this pin low causes LO-
CAL_PCI_RST# to pull low. When high, LOCAL_PCI_RST#
is the logical inverse of HEALTHY#. Tie to INTVCC if
unused.
PGI: Power Good Input. Tie this pin to the ⎯R⎯E⎯S⎯E⎯T output
of an external supply monitor or power good output of a
DC/DC converter. When all supplies have been turned on,
a timing cycle is started at the end of which the PGI pin is
sampled. If it is low, all external MOSFETs are shut off. If
the PGI Disable control bit C3 is not set, pulling this pin
low for more than 20μs during normal operation will also
shut off all MOSFETs. Tie to INTVCC if unused.
PRECHARGE: Bus Precharge Output. This pin can source
70mA at 1V as soon as 3VIN is powered-up. Leave it open
if unused.
SCL: Serial Bus Clock Input. Data at the SDA pin is shifted
in or out on rising edges of SCL. This is a high impedance
pin that is generally driven by an open-collector output
from a master controller.
SDA: Serial Bus Data Input and Output. This is a high
impedance input when address, command or data bits
are shifted in. It is an open-drain output when sending
data back to the master controller or acknowledging a
write operation. An external pull-up resistor or current
source is required.
SS: Soft-Start Input. Connect a capacitor between this pin
and ground to set the rate of increase of current limit during
start-up for dI/dt limited inrush current. When an external
MOSFET is turned on, a 20μA pull-up current charges the
capacitor. The voltage ramp on the capacitor is converted
into an internal current limit increasing linearly with time.
Leave it open if dI/dt limited inrush is not required.
TIMER: Timer Input. A capacitor between this pin and
ground sets the duration of the start-up, PGI and auto-retry
timing cycles to be 23.3ms/μF, 233ms/μF and 1.17s/μF
respectively. A timing cycle consists of TIMER being
charged to 2.56V with an internal pull-up current source
and then being reset by a switch to ground. The timing
cycle ends when TIMER falls below 0.23V. The start-up,
PGI and auto-retry timing cycles use 100μA, 10μA and
2μA pull-up current sources respectively.
VEEGATE: Gate Drive for –12V Supply External N-Chan-
nel MOSFET. An internal 20μA current source charges
the gate of the external N-channel MOSFET. An internal
clamp limits the gate voltage to 6.2V above VEEIN. During
turn-off, a 3.5mA pull-down current discharges VEEGATE
to VEEIN. During short-circuit a 65mA pull-down current
between VEEGATE and VEEIN is activated. If a –12V supply
is not available, connect VEEGATE to ground and use the
CFG pin appropriately.
VEEIN: –12V Supply, Current Sense and ADC Input. An
undervoltage lockout circuit, with 38mV hysteresis, pre-
vents any external MOSFET from turning on when this
pin is above –10.5V. The VEEIN undervoltage lockout can
be disabled by using the CFG pin. If a –12V supply is not
available, connect VEEIN to ground and use the CFG pin
appropriately.
VEEOUT: –12V Supply Foldback, ADC and Power Bad Input.
Connect this pin to the drain of the –12V supply external
N-channel MOSFET switch. Power is considered bad if this
pin rises above –11.1V. The comparator on this pin has a
built-in hysteresis of 54mV. The VEEOUT power bad function
can be disabled by using the CFG pin. This pin is also an
input to the ADC and the current limit foldback circuit. A
1800Ω active pull-up discharges VEEOUT to ground when
the external MOSFET is turned off. If a –12V supply is not
available, connect VEEOUT to ground and use the CFG pin
appropriately.
VEESENSE: –12V Supply Current Sense and ADC Input.
Connect this pin to the output of the –12V current sense
resistor. The current limit circuit controls the VEEGATE pin
to limit the sense voltage between the VEESENSE and VEEIN
pins to 50mV or less during start-up and 150mV thereafter.
During start-up a foldback feature lowers the current limit
to 16mV as the VEEOUT pin approaches ground. A circuit
breaker, enabled after start-up, trips when the sense voltage
exceeds 50mV for 22μs. To disable current limit, connect
this pin to VEEIN. If a –12V supply is not available, connect
VEESENSE to ground and use the CFG pin appropriately.
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC4245.PDF ] | |
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