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PDF LTC4215 Data sheet ( Hoja de datos )
| Número de pieza | LTC4215 | |
| Descripción | Hot Swap Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC4215/LTC4215-2
Hot Swap Controller with
I2C Compatible Monitoring
FEATURES
n Allows Safe Insertion into Live Backplane
n 8-Bit ADC Monitors Current and Voltage
n I2C/SMBus Interface
n Wide Operating Voltage Range: 2.9V to 15V
n 20μs (LTC4215) or 420μs (LTC4215-2) Circuit
Breaker Timeout
n dI/dt Controlled Soft-Start
n High Side Drive for External N-Channel MOSFET
n No External Gate Capacitor Required
n Input Overvoltage/Undervoltage Protection
n Optional Latchoff or Auto-Retry After Faults
n Alerts Host After Faults
n Inrush Current Limit with Foldback
n Available in 24-Pin (4mm × 5mm) QFN Package
n LTC4215 also available in 16-Lead Narrow SSOP
Package
APPLICATIONS
n Live Board Insertion
n Electronic Circuit Breakers
n Computers, Servers
n Platform Management
L, LT, LTC, LTM, Linear Technology, the Linear logo and Hot Swap are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patent including 7330065.
DESCRIPTION
The LTC®4215/LTC4215-2 Hot Swap™ controllers allow
a board to be safely inserted and removed from a live
backplane. Using an external N-channel pass transistor,
board supply voltage and inrush current are ramped up at
an adjustable rate. An I2C interface and onboard ADC allow
for monitoring of load current, voltage and fault status.
The device features adjustable foldback current limit and
a soft-start pin that sets the dI/dt of the inrush current.
An I2C interface may configure the part to latch off or
automatically restart after the LTC4215 detects a current
limit fault.
The controller has additional features to interrupt the host
when a fault has occurred, notify when output power is
good, detect insertion of a load card, and power-up either
automatically upon insertion or wait for an I2C command
to turn on.
The LTC4215 has a 20μs circuit breaker filter for applica-
tions that require a fast fault response time and it defaults
to latchoff after an overcurrent fault. The LTC4215-2 has
an extended 420μs circuit breaker filter for applications
where supply transients may exceed 20μs and it defaults
to restart automatically after an overcurrent fault.
TYPICAL APPLICATION
12V Application with 5A Circuit Breaker
12V
0.005Ω
FDC653N
+
VOUT
12V
34.8k
0.1μF
CL 30.1k
10Ω
SDA
SCL
ALERT
GND
BACKPLANE PLUG-IN
CARD
1.18k
P6KE16A
3.4k
INTVCC
UV VDD SENSE+ SENSE– GATE SOURCE
OV FB
SDAO
SDAI
SCL
ALERT
LTC4215UFD
EN
ADIN
INTVCC
ON TIMER SS
GPIO
GND
0.1μF
68nF
3.57k
INTVCC
24k
4215 TA01a
Start-Up Waveform
VDD
10V/DIV
INRUSH
CURRENT
2.5A/DIV
VOUT
10V/DIV
VGPIO
(POWERGOOD)
10V/DIV
CONTACT
BOUNCE
CL = 12000μF
50ms/DIV
42151 TA01b
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1
1 page  
LTC4215/LTC4215-2
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
TUE Total Unadjusted Error
VDD – SENSE
SOURCE
ADIN
l ±5.5 LSB
l ±5.0 LSB
l ±5.0 LSB
FSE Full-Scale Error
VDD – SENSE
SOURCE
ADIN
l ±5.5 LSB
l ±5.0 LSB
l ±5.0 LSB
VFS Full-Scale Voltage (255 • VLSB)
VDD – SENSE
SOURCE
ADIN
l 37.625
l 15.14
l 1.205
38.45
15.44
1.23
39.275
15.74
1.255
mV
V
V
RADIN
IADIN
I2C Interface
ADIN Pin Sampling Resistance
ADIN Pin Input Current
Conversion Rate
VADIN = 1.28V
VADIN = 1.28V
l1
l
2
0 ±0.1
10
MΩ
μA
Hz
VADR(H)
ADR0, ADR1, ADR2 Input High Voltage
l INTVCC INTVCC INTVCC
–0.8 –0.4 –0.2
V
IADR(IN,Z)
ADR0, ADR1, ADR2 Hi-Z Input Current
VADR(L)
ADR0, ADR1, ADR2 Input Low Voltage
IADR(IN)
IALERT
ADR0, ADR1, ADR2 Input Current
ALERT Input Current
VALERT(OL)
ALERT Output Low Voltage
VSDA,SCL(TH) SDA, SCL Input Threshold
ISDA,SCL(OH)
SDA, SCL Input Current
VSDA(OL)
SDA Output Low Voltage
I2C Interface Timing
ADR0, ADR1, ADR2 = 0.8V
l
ADR0, ADR1, ADR2 = INTVCC – 0.8V l
3
–3
l 0.2 0.4 0.8
ADR0, ADR1, ADR2 = 0V, INTVCC
ALERT = 6.5V
l –80
l
80
±1
IALERT = 3mA
l 0.2 0.4
l 1.3 1.7 1.9
SCL, SDA = 6.5V
l
±1
ISDA = 3mA
l 0.2 0.4
μA
μA
V
μA
μA
V
V
μA
V
fSCL(MAX)
tBUF(MIN)
tHD,STA(MIN)
tSU,STA(MIN)
tSU,STO(MIN)
tHD,DAT(MIN)
tHD,DATO
tSU,DAT(MIN)
tSP
CX
SCL Clock Frequency
Bus Free Time Between Stop/Start Condition
Hold Time After (Repeated) Start Condition
Repeated Start Condition Set-Up Time
Stop Condition Set-Up Time
Data Hold Time (Input)
Data Hold Time (Output)
Data Set-Up Time
Suppressed Spike Pulse Width
SCL, SDA Input Capacitance
Operates with fSCL ≤ fSCL(MAX)
SDAI Tied to SDAO (Note 6)
l 400 1000
l 0.12 1.3
l 30 600
l 30 600
l 140 600
l 30 100
l 300 500 900
l 30 600
l 50
110 250
l 10
kHz
μs
ns
ns
ns
ns
ns
ns
ns
pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specified.
Note 3: An internal clamp limits the GATE pin to a minimum of 5V above
SOURCE. Driving this pin to voltages beyond the clamp may damage the device.
Note 4: Offset error is the offset voltage measured from 1LSB when the
output code flickers between 0000 0000 and 0000 0001.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
precise analog input voltage. Maximum specifications are limited by the
LSB step size and the single shot measurement. Typical specifications are
measured from the 1/4, 1/2 and 3/4 areas of the quantization band.
Note 6: Guaranteed by design and not subject to test.
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5 Page 
LTC4215/LTC4215-2
OPERATION
The LTC4215 is designed to turn a board’s supply voltage
on and off in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. During
normal operation, the charge pump and gate driver turn
on an external N-channel MOSFET’s gate to pass power
to the load. The gate driver uses a charge pump that
derives its power from the VDD pin. Also included in the
gate driver is an internal 6.5V GATE-to-SOURCE clamp.
During start-up the inrush current is tightly controlled by
using current limit foldback, soft start dI/dt limiting and
output dV/dt limiting.
The current sense (CS) amplifier monitors the load current
using the difference between the SENSE+ (VDD for SSOP)
and SENSE– pin voltages. The CS amplifier limits the cur-
rent in the load by pulling back on the GATE-to-SOURCE
voltage in an active control loop when the sense voltage
exceeds the commanded value. The CS amplifier requires
20μA input bias current from both the SENSE+ and the
SENSE– pins.
A short circuit on the output to ground results in excessive
power dissipation during active current limiting. To limit
this power, the CS amplifier regulates the voltage between
the SENSE+ and SENSE– pins at 75mV.
If an overcurrent condition persists, the internal circuit
breaker (CB) registers a fault when the sense voltage ex-
ceeds 25mV for more than 20μs in the case of the LTC4215
or 420μs in the case of the LTC4215-2. This indicates to
the logic that it is time to turn off the GATE to prevent
overheating. At this point the start-up TIMER pin voltage
ramps down using the 2μA current source until the volt-
age drops below 0.2V (comparator TM1) which tells the
logic that the pass transistor has cooled and it is safe to
turn it on again if overcurrent auto-retry is enabled. If the
TIMER pin is tied to INTVCC, the cool-down time defaults
to 5 seconds on an internal system timer in the logic.
The output voltage is monitored using the FB pin and the
Power Good (PG) comparator to determine if the power
is available for the load. The power good condition can be
signaled by the GPIO pin using an open-drain pulldown
transistor. The GPIO pin may also be configured to signal
power bad, or as a general purpose input (GP comparator),
or a general purpose open drain output.
The Functional Diagram shows the monitoring blocks of
the LTC4215. The group of comparators on the left side
includes the undervoltage (UV), overvoltage (OV), reset
(RST), enable (EN) and signal on (ON) comparators. These
comparators determine if the external conditions are valid
prior to turning on the GATE. But first the two undervoltage
lockout circuits, UVLO1 and UVLO2, validate the input
supply and the internally generated 3.1V supply, INTVCC.
UVLO2 also generates the power-up initialization to the
logic circuits as INTVCC crosses this rising threshold. If the
fixed internal overvoltage comparator, OV2, detects that
VDD is greater than 15.6V, the part immediately generates
an overvoltage fault and turns the GATE off.
Included in the LTC4215 is an 8-bit A/D converter. The con-
verter has a 3-input multiplexer to select between the ADIN
pin, the SOURCE pin and the VDD – SENSE voltage.
An I2C interface is provided to read the A/D registers. It
also allows the host to poll the device and determine if
faults have occurred. If the ALERT line is configured as an
interrupt, the host is enabled to respond to faults in real
time. The typical SDA line is divided into an SDAI (input)
and SDAO (output). This simplifies applications using an
optoisolator driven directly from the SDAO output. An ap-
plication which uses optoisolation is shown in Figure 14.
The I2C device address is decoded using the ADR0, ADR1
and ADR2 pins. These inputs have three states each that
decode into a total of 27 device addresses. ADR1 and
ADR2 are not available in the SSOP package; therefore,
those pins are NC in the address map.
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11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC4215.PDF ] | |
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