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PDF LTC3835 Data sheet ( Hoja de datos )
| Número de pieza | LTC3835 | |
| Descripción | Low IQ Synchronous Step-Down Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
www.datasheet4u.com
n Wide Output Voltage Range: 0.8V ≤ VIN ≤ 10V
n Low Operating Quiescent Current: 80μA
n OPTI-LOOP® Compensation Minimizes COUT
n ±1% Output Voltage Accuracy
n Wide VIN Range: 4V to 36V Operation
n Phase-Lockable Fixed Frequency 140kHz to 650kHz
n Dual N-Channel MOSFET Synchronous Drive
n Very Low Dropout Operation: 99% Duty Cycle
n Adjustable Output Voltage Soft-Start or Tracking
n Output Current Foldback Limiting
n Power Good Output Voltage Monitor
n Clock Output for PolyPhase® Applications
n Output Overvoltage Protection
n Low Shutdown IQ: 10μA
n Internal LDO Powers Gate Drive from VIN or VOUT
n Selectable Continuous, Pulse-Skipping or
Burst Mode® Operation at Light Loads
n Small 20-Lead TSSOP or 4mm × 5mm QFN Package
APPLICATIONS
n Automotive Systems
n Telecom Systems
n Battery-Operated Digital Devices
n Distributed DC Power Systems
LTC3835
Low IQ Synchronous
Step-Down Controller
DESCRIPTION
The LTC®3835 is a high performance step-down switching
regulator controller that drives an all N-channel synchro-
nous power MOSFET stage. A constant-frequency current
mode architecture allows a phase-lockable frequency of
up to 650kHz.
The 80μA no-load quiescent current extends operating
life in battery powered systems. OPTI-LOOP compensa-
tion allows the transient response to be optimized over
a wide range of output capacitance and ESR values. The
LTC3835 features a precision 0.8V reference and a power
good output indicator. The 4V to 36V input supply range
encompasses a wide range of battery chemistries.
The TRACK/SS pin ramps the output voltage during start-
up. Current foldback limits MOSFET heat dissipation during
short-circuit conditions.
Comparison of LTC3835 and LTC3835-1
PART #
LTC3835
CLKOUT/
PHASMD
YES
EXTVCC
YES
PGOOD
YES
LTC3835-1 NO NO NO
PACKAGES
FE20/4 × 5 QFN
GN16/3 × 5 DFN
L, LT, LTC, LTM, Burst Mode, PolyPhase and OPTI-LOOP are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents including 5408150, 5481178, 5705919, 5929620,
6304066, 6498466, 6580258, 6611131.
TYPICAL APPLICATION
High Efficiency Synchronous Step-Down Converter
0.01μF
330pF
33k
20k
62.5k
CLKOUT
PLLLPF
RUN
VIN
TG
PGOOD
TRACK/SS
BOOST
ITH
LTC3835
SW
100pF
SGND
PLLIN/MODE
VFB
SENSE–
SENSE+
INTVCC
EXTVCC
BG
PGND
0.22μF
10μF
3.3μH 0.012Ω
4.7μF
VIN
4V TO
36V
VOUT
3.3V
5A
150μF
3835 TA01
Efficiency and Power Loss
vs Load Current
100 100000
90 EFFICIENCY
VIN = 12V; VOUT = 3.3V
10000
80
70 1000
60
50 100
40
30 POWER LOSS 10
20 1
10
0
0.001 0.01
0.1 1 10 100
LOAD CURRENT (mA)
0.1
1000 10000
3835 TA01b
3835fc
1
1 page  
LTC3835
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25ºC, unless otherwise noted.
Efficiency and Power Loss
vs Output Current
www.data10s0heet4u.cBoumrst Mode OPERATION
90 FORCED CONTINUOUS MODE
PULSE SKIPPING MODE
80
10000
1000
70
60 100
50
40
30 VIN = 12V
VOUT = 3.3V
20
10
1
10
0
0.001 0.01 0.1 1 10 100
LOAD CURRENT (mA)
FIGURE 11 CIRCUIT
0.1
1000 10000
3835 G01
Efficiency vs Load Current
100
VIN = 12V
VIN = 5V
90 VOUT = 3.3V
80
70
60
50
40
0.001 0.01 0.1 1 10 100
LOAD CURRENT (mA)
FIGURE 11 CIRCUIT
1000 10000
3835 G02
Efficiency vs Input Voltage
98
96
94
92
90
88
86
84
VOUT = 3.3V
82
0 5 10 15 20 25 30
INPUT VOLTAGE (V)
FIGURE 11 CIRCUIT
35 40
3835 G03
Load Step
(Burst Mode Operation)
Load Step
(Forced Continuous Mode)
Load Step
(Pulse-Skipping Mode)
VOUT
100mV/
DIV AC
COUPLED
IL
2A/DIV
20μs/DIV
FIGURE 11 CIRCUIT
VOUT = 3.3V
VOUT
100mV/DIV
AC
COUPLED
3835 G04
IL
2A/DIV
20μs/DIV
FIGURE 11 CIRCUIT
VOUT = 3.3V
VOUT
100mV/DIV
AC
COUPLED
3835 G05
IL
2A/DIV
20μs/DIV
FIGURE 11 CIRCUIT
VOUT = 3.3V
3835 G06
Inductor Current at Light Load
FORCED
CONTIN-
UOUS
MODE
2A/DIV
BURST
MODE
PULSE-
SKIPPING
MODE
4μs/DIV
FIGURE 11 CIRCUIT
VOUT = 3.3V
ILOAD = 300μA
3835 G07
Soft Start-Up
VOUT
1V/DIV
Tracking Start-Up
VOUT2
2V/DIV (MASTER)
VOUT1
2V/DIV
(SLAVE)
20ms/DIV
FIGURE 11 CIRCUIT
3835 G08
20ms/DIV
FIGURE 11 CIRCUIT
3835 G09
3835fc
5
5 Page 
LTC3835
OPERATION (Refer to Functional Diagram)
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping, or Continuous Conduction)
www(.dPaLtaLsIhNe/eMt4uO.cDoEm Pin)
The LTC3835 can be enabled to enter high efficiency Burst
Mode operation, constant-frequency pulse-skipping mode,
or forced continuous conduction mode at low load currents.
To select Burst Mode operation, tie the PLLIN/MODE pin
to a DC voltage below 0.8V (e.g., SGND). To select forced
continuous operation, tie the PLLIN/MODE pin to INTVCC. To
select pulse-skipping mode, tie the PLLIN/MODE pin to a DC
voltage greater than 0.8V and less than INTVCC – 0.5V.
When the LTC3835 is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-tenth of the maximum sense voltage even though the
voltage on the ITH pin indicates a lower value. If the aver-
age inductor current is lower than the load current, the
error amplifier EA will decrease the voltage on the ITH pin.
When the ITH voltage drops below 0.4V, the internal sleep
signal goes high (enabling “sleep” mode) and both external
MOSFETs are turned off. The ITH pin is then disconnected
from the output of the EA and “parked” at 0.425V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3835 draws to
only 80μA. In sleep mode, the load current is supplied by
the output capacitor. As the output voltage decreases, the
EA’s output begins to rise. When the output voltage drops
enough, the ITH pin is reconnected to the output of the
EA, the sleep signal goes low, and the controller resumes
normal operation by turning on the top external MOSFET
on the next cycle of the internal oscillator.
When the LTC3835 is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (RICMP) turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative, thus
operating in discontinuous operation.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by the
voltage on the ITH pin, just as in normal operation. In this
mode, the efficiency at light loads is lower than in Burst
Mode operation. However, continuous operation has the
advantages of lower output ripple and less interference
to audio circuitry. In forced continuous mode, the output
ripple is independent of load current.
When the PLLIN/MODE pin is connected for pulse-skipping
mode or clocked by an external clock source to use the phase-
locked loop (see Frequency Selection and Phase-Locked
Loop section), the LTC3835 operates in PWM pulse-skipping
mode at light loads. In this mode, constant-frequency opera-
tion is maintained down to approximately 1% of designed
maximum output current. At very light loads, the current
comparator ICMP may remain tripped for several cycles and
force the external top MOSFET to stay off for the same number
of cycles (i.e., skipping pulses). The inductor current is not
allowed to reverse (discontinuous operation). This mode,
like forced continuous operation, exhibits low output ripple
as well as low audio noise and reduced RF interference as
compared to Burst Mode operation. It provides higher low
current efficiency than forced continuous mode, but not
nearly as high as Burst Mode operation.
Frequency Selection and Phase-Locked Loop
(PLLLPF and PLLIN/MODE Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3835’s controllers can
be selected using the PLLLPF pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the PLLLPF pin can be floated, tied to INTVCC,
or tied to SGND to select 400kHz, 530kHz, or 250kHz,
respectively.
A phase-locked loop (PLL) is available on the LTC3835
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. In this
case, a series R-C should be connected between the PLLLPF
pin and SGND to serve as the PLL’s loop filter. The LTC3835
phase detector adjusts the voltage on the PLLLPF pin to
align the turn-on of the external top MOSFET to the rising
edge of the synchronizing signal.
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11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC3835.PDF ] | |
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