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PDF LTC2299 Data sheet ( Hoja de datos )
| Número de pieza | LTC2299 | |
| Descripción | 80Msps Low Power 3V ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
www.datasheet4u.com
■ Integrated Dual 14-Bit ADCs
■ Sample Rate: 80Msps
■ Single 3V Supply (2.7V to 3.4V)
■ Low Power: 444mW
■ 73dB SNR at 70MHz Input
■ 90dB SFDR at 70MHz Input
■ 110dB Channel Isolation at 100MHz
■ Multiplexed or Separate Data Bus
■ Flexible Input: 1VP-P to 2VP-P Range
■ 575MHz Full Power Bandwidth S/H
■ Clock Duty Cycle Stabilizer
■ Shutdown and Nap Modes
■ Pin Compatible Family
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)
■ 64-Pin (9mm × 9mm) QFN Package
U
APPLICATIO S
■ Wireless and Wired Broadband Communication
■ Imaging Systems
■ Spectral Analysis
■ Portable Instrumentation
TYPICAL APPLICATIO
ANALOG
INPUT A
+
INPUT
S/H
–
14-BIT
PIPELINED
ADC CORE
CLK A
CLK B
CLOCK/DUTY CYCLE
CONTROL
CLOCK/DUTY CYCLE
CONTROL
ANALOG
INPUT B
+
INPUT
S/H
–
14-BIT
PIPELINED
ADC CORE
LTC2299
Dual 14-Bit, 80Msps
Low Power 3V ADC
DESCRIPTIO
The LTC®2299 is a 14-bit 80Msps, low power dual 3V
A/D converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2299 is perfect for
demanding imaging and communications applications
with AC performance that includes 73dB SNR and 90dB
SFDR for signals well beyond the Nyquist frequency.
DC specs include ±1.2LSB INL (typ), ±0.5LSB DNL (typ)
and ±5LSB INL, ±1LSB DNL over temperature. The transi-
tion noise is a low 1.2LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic. An optional multiplexer allows both channels to
share a digital output bus.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
OUTPUT
DRIVERS
OVDD
D13A
•••
D0A
OGND
MUX
OUTPUT
DRIVERS
OVDD
D13B
•••
D0B
OGND
2299 TA01
SNR vs Input Frequency,
–1dB, 2V Range
75
74
73
72
71
70
69
68
67
66
65
0
50 100 150
INPUT FREQUENCY (MHz)
200
2299 TA02
2299fa
1
1 page  
LTC2299
POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
www.VdDaDtasheet4u.com Analog Supply Voltage
OVDD
Output Supply Voltage
IVDD Supply Current
PDISS
Power Dissipation
PSHDN
Shutdown Power (Each Channel)
PNAP Nap Mode Power (Each Channel)
CONDITIONS
(Note 9)
(Note 9)
Both ADCs at fS(MAX)
Both ADCs at fS(MAX)
SHDN = H, OE = H, No CLK
SHDN = H, OE = L, No CLK
MIN TYP MAX
● 2.7 3 3.4
● 0.5 3 3.6
● 148 172
● 444 516
2
15
UNITS
V
V
mA
mW
mW
mW
WU
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
fs
tL
PARAMETER
Sampling Frequency
CLK Low Time
tH CLK High Time
tAP
tD
tMD
Pipeline Latency
Sample-and-Hold Aperture Delay
CLK to DATA Delay
MUX to DATA Delay
Data Access Time After OE↓
BUS Relinquish Time
CONDITIONS
(Note 9)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On (Note 9)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On (Note 9)
CL = 5pF (Note 7)
CL = 5pF (Note 7)
CL = 5pF (Note 7)
(Note 7)
MIN TYP MAX
●1
80
● 5.9 6.25 500
● 5 6.25 500
● 5.9 6.25 500
● 5 6.25 500
0
● 1.4 2.7 5.4
● 1.4 2.7 5.4
● 4.3 10
● 3.3 8.5
5
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 80MHz, input range = 2VP-P with differential
drive, unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 80MHz, input range = 1VP-P with differential
drive. The supply current and power dissipation are the sum total for both
channels with both channels active.
Note 9: Recommended operating conditions.
2299fa
5
5 Page 
LTC2299
APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE
wwwS.diagtansahle-etot4-uN.cooimse Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1)
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Aperture Delay Time
The time from when CLK reaches midsupply to the instant
that the input signal is held by the sample and hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
Crosstalk
Crosstalk is the coupling from one channel (being driven
by a full-scale signal) onto the other channel (being driven
by a –1dBFS signal).
CONVERTER OPERATION
As shown in Figure 1, the LTC2299 is a dual CMOS
pipelined multistep converter. The converter has six
pipelined ADC stages; a sampled analog input will result in
a digitized value five cycles later (see the Timing Diagram
section). For optimal AC performance the analog inputs
should be driven differentially. For cost sensitive
2299fa
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC2299.PDF ] | |
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