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PDF LTC2254 Data sheet ( Hoja de datos )
| Número de pieza | LTC2254 | |
| Descripción | (LTC2254 / LTC2255) 125/105Msps Low Power 3V ADCs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2254 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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FEATURES
www.datasheet4u.com
■ Sample Rate: 125Msps/105Msps
■ Single 3V Supply (2.85V to 3.4V)
■ Low Power: 395mW/320mW
■ 72.4dB SNR
■ 88dB SFDR
■ No Missing Codes
■ Flexible Input: 1VP-P to 2VP-P Range
■ 640MHz Full Power Bandwidth S/H
■ Clock Duty Cycle Stabilizer
■ Shutdown and Nap Modes
■ Pin Compatible Family
125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit)
105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit)
80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit)
65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit)
40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit)
25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit)
10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit)
■
32-Pin
(5mm
×
5mm)
U
QFN
Package
APPLICATIO S
■ Wireless and Wired Broadband Communication
■ Imaging Systems
■ Ultrasound
■ Spectral Analysis
■ Portable Instrumentation
LTC2255/LTC2254
14-Bit, 125/105Msps
Low Power 3V ADCs
DESCRIPTIO
The LTC®2255/LTC2254 are 14-bit 125Msps/105Msps,
low power 3V A/D converters designed for digitizing high
frequency, wide dynamic range signals. The LTC2255/
LTC2254 are perfect for demanding imaging and commu-
nications applications with AC performance that includes
72.3dB SNR and 85dB SFDR for signals at the Nyquist
frequency.
DC specs include ±1LSB INL (typ), ±0.5LSB DNL (typ) and
no missing codes over temperature. The transition noise
is a low 1.3 LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.3V
logic.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
REFH
REFL
FLEXIBLE
REFERENCE
ANALOG
INPUT
+
INPUT
S/H
–
14-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
CLOCK/DUTY
CYCLE
CONTROL
CLK
OUTPUT
DRIVERS
OVDD
D13
•
•
•
D0
OGND
22554 TA01a
LTC2255: SNR vs Input Frequency,
–1dB, 2V Range, 125Msps
75
74
73
72
71
70
69
68
67
66
65
0
50 100 150 200 250 300 350
INPUT FREQUENCY (MHz) 33554 G09
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1
1 page  
LTC2255/LTC2254
WU
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
wwwf.sdatasheet4u.comSampling Frequency
tL CLK Low Time
tH CLK High Time
tAP Sample-and-Hold
Aperture Delay
tD CLK to DATA delay
Data Access Time
After OE↓
BUS Relinquish Time
Pipeline Latency
CONDITIONS
(Note 9)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
CL = 5pF (Note 7)
CL = 5pF (Note 7)
(Note 7)
LTC2255
MIN TYP MAX
●1
125
● 3.8 4 500
●3
4 500
LTC2254
MIN TYP MAX
1 105
4.5 4.76 500
3 4.76 500
UNITS
MHz
ns
ns
● 3.8 4 500 4.5 4.76 500
●3
4 500 3 4.76 500
ns
ns
0 0 ns
● 1.4 2.7 5.4 1.4 2.7 5.4
● 4.3 10
4.3 10
ns
ns
● 3.3 8.5
5
3.3 8.5
ns
5 Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 125MHz (LTC2255) or 105MHz (LTC2254),
input range = 2VP-P with differential drive, clock duty cycle stabilizer on,
unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 125MHz (LTC2255) or 105MHz (LTC2254),
input range = 1VP-P with differential drive.
Note 9: Recommended operating conditions.
22554fa
5
5 Page 
W
FUNCTIONAL BLOCK DIAGRA
LTC2255/LTC2254
AIN+
INPUT
www.datasAIhN–eet4u.cSo/Hm
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
VCM
2.2µF
1.5V
REFERENCE
RANGE
SELECT
SENSE
REF
BUF
SHIFT REGISTER
AND CORRECTION
REFH
REFL INTERNAL CLOCK SIGNALS
DIFF
CLOCK/DUTY
CONTROL
REF
CYCLE
LOGIC
AMP CONTROL
REFH 0.1µF REFL
2.2µF
1µF 1µF
CLK
M0DE SHDN
OE
Figure 1. Functional Block Diagram
OUTPUT
DRIVERS
OVDD
OF
D13
•
•
•
D0
OGND
22554 BD01
WU W
TI I G DIAGRA
ANALOG
INPUT
CLK
D0-D13, OF
tAP
N
tH N + 1
tL
Timing Diagram
N+2
N+3
N+4
N+5
tD
N–5
N–4
N–3
N–2
N–1
N
22554 TD01
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11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC2254.PDF ] | |
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