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PDF MAX3625 Data sheet ( Hoja de datos )
| Número de pieza | MAX3625 | |
| Descripción | Precision Clock Generator | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-1010; Rev 0; 10/07
Low-Jitter, Precision Clock Generator
with Three Outputs
www.datasheet4u.com
General Description
The MAX3625 is a low-jitter precision clock generator
optimized for networking applications. The device inte-
grates a crystal oscillator and a phase-locked loop
(PLL) clock multiplier to generate high-frequency clock
outputs for Ethernet, 10G Fibre Channel, and other net-
working applications.
Maxim’s proprietary PLL design features ultra-low jitter
and excellent power-supply noise rejection, minimizing
design risk for network equipment.
The MAX3625 has three LVPECL outputs. Selectable
output dividers and a selectable feedback divider allow
a range of output frequencies.
Features
♦ Crystal Oscillator Interface: 24.8MHz to 27MHz
♦ CMOS Input: Up to 320MHz
♦ Output Frequencies
Ethernet: 125MHz, 156.25MHz, 312.5MHz
10G Fibre Channel: 159.375MHz, 318.75MHz
♦ Low Jitter
0.14psRMS (1.875MHz to 20MHz)
0.38psRMS (12kHz to 20MHz)
♦ Excellent Power-Supply Noise Rejection
♦ No External Loop Filter Capacitor Required
Applications
Ethernet Networking Equipment
Fibre Channel Storage Area Network
Pin Configuration and Typical Application Circuit appear at
end of data sheet.
IN_SEL
MR
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX3625CUG+ 0°C to +70°C 24 TSSOP
+Denotes a lead-free package.
PKG
CODE
U24-1
BYPASS
SELA[1:0]
Block Diagram
REF_IN
27pF
X_IN
X_OUT
33pF
SELA[1:0]
SELB[1:0]
FB_SEL
BYPASS
RESET LOGIC/POR
RESET
LVCMOS
0
CRYSTAL
OSCILLATOR
1
DIVIDERS:
M = 24, 25
NA = 1, 2, 4, 5
NB = 1, 2, 4, 5
0
620MHz TO 648MHz
PFD
FILTER
VCO
1
RESET
DIVIDER
M
MAX3625
DIVIDER
NA
RESET
LVPECL
BUFFER
RESET
DIVIDER
NB
LVPECL
BUFFER
LVPECL
BUFFER
QA_OE
QA
QA
QB1
QB1
QB_OE
QB0
QB0
FB_SEL
SELB[1:0]
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
Low-Jitter, Precision Clock Generator
with Three Outputs
www.datasheet4u.com
PIN
1, 24
NAME
SELB0,
SELB1
2 BYPASS
3 MR
4 VCCO_A
5 QA
6 QA
7 QB_OE
8 QA_OE
9 FB_SEL
10
11
12, 13
14
15
16
17
18
19
20
21
22
23
VCCA
VCC
SELA0,
SELA1
GND
X_OUT
X_IN
REF_IN
IN_SEL
QB1
QB1
QB0
QB0
VCCO_B
Pin Description
FUNCTION
LVCMOS/LVTTL Inputs. Control NB divider setting. Has 50kΩ input impedance. See Table 2 for more
information.
LVCMOS/LVTTL Input (Active Low). Connect low to bypass the internal PLL. Connect high or leave open
for normal operation. When in bypass mode the output dividers are set to divide by 1. Has internal 75kΩ
pullup to VCC.
LVCMOS/LVTTL Input. Master reset input. Pulse high for > 1µs to reset all dividers. Has internal 75kΩ
pulldown to GND. Not required for normal operation.
Power Supply for QA Clock Output. Connect to +3.3V.
Noninverting Clock Output, LVPECL
Inverting Clock Output, LVPECL
LVCMOS/LVTTL Input. Enables/disables QB clock outputs. Connect pin high or leave open to enable
LVPECL clock outputs QB0 and QB1. Connect low to set QB0 and QB1 to a logic 0. Has internal 75kΩ
pullup to VCC.
LVCMOS/LVTTL Input. Enables/disables the QA clock output. Connect this pin high or leave open to
enable the LVPECL clock output QA. Connect low to set QA to a logic 0. Has internal 75kΩ pullup to VCC.
LVCMOS/LVTTL Input. Controls M divider setting. See Table 3 for more information. Has internal 75kΩ
pulldown to GND.
Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering, this pin
can connect to VCC through 10.5Ω as shown in Figure 1 (requires VCC = 3.3V ±5%).
Core Power Supply. Connect to +3.3V.
LVCMOS/LVTTL Inputs. Control NA divider setting. See Table 2 for more information. 50kΩ input
impedance.
Supply Ground
Crystal Oscillator Output
Crystal Oscillator Input
LVCMOS Reference Clock Input. Self-biased to allow AC- or DC-coupling.
LVCMOS/LVTTL Input. Connect high or leave open to use a crystal. Connect low to use REF_IN. Has
internal 75kΩ pullup to VCC.
LVPECL, Inverting Clock Output
LVPECL, Noninverting Clock Output
LVPECL, Inverting Clock Output
LVPECL, Noninverting Clock Output
Power Supply for QB0 and QB1 Clock Output. Connect to +3.3V.
_______________________________________________________________________________________ 5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet MAX3625.PDF ] | |
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