PDF ACS8527 Data sheet ( Hoja de datos )

Número de pieza	ACS8527
Descripción	Line Card Protection Switch
Fabricantes	Semtech Corporation
Logotipo
Hay una vista previa y un enlace de descarga de ACS8527 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas
No Preview Available ! ACS8527 MUXPLL Line Card Protection Switch for PDH, SONET or SDH Systems ADVANCED COMMUNICATIONS Deswcwrwi.pDattiaoSnheet4U.com FINAL Features DATASHEET The ACS8527 is a highly integrated, single-chip, MUX with PLL solution for protection switching between two SECs (SDH/SONET Equipment Clocks) from Master and Slave SETS (Synchronous Equipment Timing Source) clock cards, for line cards in a PDH, SONET or SDH Network Element. The ACS8527 has fast activity monitors on the inputs and will raise a flag on a pin if there is a loss of activity on the currently selected input. The protection switching between the input reference clock sources is controlled by an external pin. The ACS8527 has two SEC reference clock input ports, configured for expected frequency by setting hardware pins. The ACS8527 can perform frequency translation, converting, for example, an 8 kHz SEC input clock from a backplane into a 155.52 MHz clock for local line cards. The ACS8527 generates two independent SEC clock outputs, one on a LVDS port and one on a TTL/CMOS port, at spot frequencies configured by hardware pins. The spot frequencies range from 1.544 MHz up to 155.52 MHz. The ACS8527 also provides an 8 kHz Frame Sync output and 2 kHz Multi-Frame Sync output. Block Diagram Line card protection switch - partners Semtech SETS devices for Stratum 3E/3/4E/4 PDH, SONET or SDH applications High performance DPLL/APLL solution Output jitter compliant to STM-1 Two independent SEC inputs ports (TTL) Four independent output ports: Two clock ports: one LVDS, one TTL Two Syncs (TTL): 8 kHz FrSync & 2 KHz MFrSync I/O frequencies configurable via hardware pins: TTL I/O ports: spot frequencies 1.544 MHz to 77.76 MHz LVDS output port: spot frequencies 19.44 MHz to 155.52 MHz Digital Holdover mode on input failure “Loss of activity” on selected input flagged on dedicated pin Source switch under external hardware control 7O Hz (acquisition) /35 Hz (locked) DPLL bandwidth Output clock phase continuity to GR-1244-CORE[13] Single 3.3 V operation, 5 V I/O compatible IEEE 1149.1 JTAG Boundary Scan is supported Operating temperature (ambient) of -40 to +85°C Available in LQFP 64 package Lead (Pb)-free version available (ACS8527T). RoHS and WEE compliant Figure 1 Block Diagram of the ACS8527 MUXPLL IP_FREQ SONSDHB SRCSW 2 x SEC TTL inputs SEC Inputs: SEC1 Input Frequencies 8kHz 1.544 MHz 2.048 MHz SEC2 6.48 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz TCK 77.76 MHz TDI TMS TRST TDO Input SEC Port Selector IEEE 1149.1 JTAG Revision 4.01/June 2006 © Semtech Corp. DPLL APLL Output Port Frequency Selection Chip Clock Generator TCXO or XO Page 1 OP_FREQ1 OP_FREQ2 LOS_ALARM SEC Outputs: 01 (LVDS) 02 (TTL) Sync Outputs: MFrSync 2 kHz (TTL) FrSync 8 kHz (TTL) Output Frequencies/MHz 01 Output: 02 Output: 19.44 1.544 25.92 2.048 34.368 (E3) 3.088 38.88 19.44 44.736 (DS3) 25.92 51.84 34.368 (E3) 77.76 38.88 155.52 44.736 (DS3) 51.84 77.76 F8527D_001BLOCKDIA_01 www.semtech.com 1 page ACS8527 MUXPLL ADVANCED COMMUNICATIONS Tableww3w.ODathtaeSrhePeitn4Us.com Pin Number Symbol I/O Type 5 LOS_ALARM O TTL/CMOS 6 REFCLK I TTL 13 SRCSW I TTLD 17 FrSync O TTL/CMOS 18 MFrSync O TTL/CMOS 19, O1POS, 20 O1NEG O LVDS 28 IP_FREQ0 I TTLD 29 SEC1 I TTLD 30 SEC2 I TTLD 33 IP_FREQ1 I TTLD 34 IP_FREQ2 I TTLD 35 O2_FREQ0 I TTLD 36 O2_FREQ2 I TTLD 37 TRST I TTLD 38 O2_FREQ1 I TTLD 41 TMS I TTLD 45 O1_FREQ0 I TTLU 46 O1_FREQ1 I TTLU 48 PORB I TTLU 49 TCK 50 TDO I TTLD O TTL/CMOS 51 TDI I TTLD 56 O2 O TTL/CMOS 63 O1_FREQ2 I TTLU 64 SONSDHB I TTLD FINAL DATASHEET Description Loss Of Signal Alarm: Flag to indicate loss of activity of currently selected reference source is raised on this pin. Reference Clock: 12.800 MHz (refer to section headed Local Oscillator Clock). Source Switching: Controls switchover between SEC1 and SEC2 inputs as the selected reference. SRCSW must be held High on power-up or reset, and for a further 251 ms after PORB has gone High. See “Initialization” on page 7. Output Reference: 8 kHz Frame Sync output. Output Reference: 2 kHz Multi-Frame Sync output. Output Reference 1: Differential output. LVDS. Input Reference Frequency Select: Frequency select for input SEC1 and SEC2. Input Reference 1: Primary input. Input Reference 2: Secondary input. Input Reference Frequency Select: Frequency select for input SEC1 and SEC2. Input Reference Frequency Select: Frequency select for input SEC1 and SEC2. Output O2 Frequency Select: Frequency select for output O2. Output O2 Frequency Select: Frequency select for output O2. JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode. TRST = 0 for normal device operation (JTAG logic transparent). NC if not used. Output O2 Frequency Select: Frequency select for output O2. JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of TCK. NC if not used. Output O1 Frequency Select: Frequency select for output O1. Output O1 Frequency Select: Frequency select for output O1. Power-On Reset: Master reset. If PORB is forced Low, all internal states are reset back to default values. JTAG Clock: Boundary Scan clock input. JTAG Output: Serial test data output. Updated on falling edge of TCK. JTAG Input: Serial test data Input. Sampled on rising edge of TCK. NC if not used. Output Reference: Programmable, default 19.44 MHz. Output O1 Frequency Select: Frequency select for output O1. SONET or SDH frequency select: Sets the device for SONET or SDH frequencies on power-up/reset. Revision 4.01/June 2006 © Semtech Corp. Page 5 www.semtech.com 5 Page ACS8527 MUXPLL ADVANCED COMMUNICATIONS Maxwiwmw.DuamtaShReeat4tUin.cogms FINAL DATASHEET Important Note: The Absolute Maximum Ratings, Table 8, are stress ratings only, and functional operation of the device at conditions other than those indicated in the Operating Conditions sections of this specification are not implied. Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product. Table 8 Absolute Maximum Ratings Parameter Supply Voltage VDD1, VDD2, VDD3, VD1+,VD2+, VD3+, VA1+, VA2+, VA3+, VDD_DIFF Input Voltage (non-supply pins) Output Voltage (non-supply pins) Ambient Operating Temperature Range Storage Temperature Symbol VDD VIN VOUT TA TSTOR Minimum -0.5 - - -40 -50 Maximum 3.6 5.5 5.5 +85 +150 Units V V V oC oC Operating Conditions Table 9 Operating Conditions Parameter Power Supply (dc voltage) VDD1, VDD2, VDD3, VD1+,VD2+, VD3+, VA1+, VA2+, VA3+, VDD_DIFF Power Supply (dc voltage) VDD5V Ambient Temperature Range Supply Current (Typical - one 19 MHz output) Total Power Dissipation Symbol VDD VDD5V TA IDD PTOT Minimum 3.0 3.0 -40 - - Typical 3.3 3.3/5.0 - 110 360 Maximum 3.6 5.5 +85 200 720 Units V V oC mA mW DC Characteristics Table 10 DC Characteristics: TTL Input Port Across all operating conditions, unless otherwise stated PARAMETER Symbol VIN High VIN Low Input Current VIH VIL IIN Revision 4.01/June 2006 © Semtech Corp. Minimum 2 - - Page 11 Typical - - - Maximum - 0.8 10 Units V V µA www.semtech.com 11 Page

Páginas	Total 22 Páginas
PDF Descargar	[ Datasheet ACS8527.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
ACS8520	Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems	Semtech Corporation
ACS8522	Synchronous Equipment Timing Source	Semtech Corporation
ACS8522A	Synchronous Equipment Timing Source	Semtech Corporation
ACS8525	Line Card Protection Switch	Semtech Corporation

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar