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PDF ISL6537 Data sheet ( Hoja de datos )
| Número de pieza | ISL6537 | |
| Descripción | ACPI Regulator/Controller | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
February 8, 2005
ISL6537
FN9142.4
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6537 provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
supply VDDQ during S0/S1 and S3 states. During S0/S1
state, a fully integrated sink-source regulator generates an
accurate (VDDQ/2) high current VTT voltage without the
need for a negative supply. A buffered version of the VDDQ/2
www.DataShereeft4eUre.cnocme is provided as VREF. Two LDO controllers are also
integrated for the GMCH core voltage regulation and for the
GMCH and CPU VTT termination voltage regulation.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
±2% over line, load, and temperature ranges. The output is
user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
indicates that the GMCH and CPU VTT termination voltage
is within spec and operational.
Each output is monitored for undervoltage events. The
switching regulator also has overvoltage and over current
protection. Thermal shutdown is integrated.
Pinout
ISL6537 (6x6 QFN)
TOP VIEW
28 27 26 25 24 23 22
5VSBY 1
21 DRIVE4
S3# 2
20 REFADJ4
P12V 3
GND 4
DDR_VTT 5
GND
29
19 DRIVE3
18 FB3
17 FB4
DDR_VTT 6
16 COMP
VDDQ 7
15 FB
8 9 10 11 12 13 14
Features
• Generates 4 Regulated Voltages
- Synchronous Buck PWM Controller for DDR VDDQ
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference for DDR VTT
- LDO Regulator for GMCH Core
- LDO Regulator for CPU/GMCH VTT Termination
• ACPI compliant sleep state control
• Glitch-free Transitions During State Changes
• Integrated VREF Buffer
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
- All Outputs: ±2% Over Temperature
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Over-voltage Monitoring on All Outputs
• OCP on the Switching Regulator
• Integrated Thermal Shutdown Protection
• Pb-Free Available (RoHS Compliant)
Applications
• Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
• Graphics cards - GPU and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
Ordering Information
TEMP. RANGE
PART NUMBER
(°C)
PACKAGE
PKG.
DWG. #
ISL6537CR
0 to 70
28 Ld 6x6 QFN L28.6x6
ISL6537CRZ
(See Note)
0 to 70
28 Ld 6x6 QFN L28.6x6
(Pb-free)
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6537
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
VTT REGULATOR
Upper Divider Impedance
Lower Divider Impedance
VREF_OUT Buffer Source Current
Maximum VTT Load Current
RU - 2.5 -
RL - 2.5 -
IVREF_OUT
- -2
IVTT_MAX
Periodic load applied with 30% duty cycle -3
-
3
and 10ms period using
ISL6537_6506EVAL1 evaluation board
(see Application Note AN1123)
kΩ
kΩ
mA
A
LINEAR REGULATORS
www.DataSheDetC4UG.cAoINm
Gain Bandwidth Product
GBWP
Guaranteed By Design
- 80
15 -
-
-
dB
MHz
Slew Rate
SR
- 6 - V/µs
DRIVEn High Output Voltage
DRIVEn unloaded
9.75 10.0
-
V
DRIVEn Low Output Voltage
- 0.16 0.50
V
DRIVEn High Output Source Current
DRIVEn Low Output Sink Current
VIDPGD
VFB = 770mV; VDRIVEn = 0V
VFB = 830mV; VDRIVEn = 10V
- 1.7 2.6 mA
-
1.2 1.75
mA
VTT_GMCH/CPU Rising Threshold
VTT_GMCH/CPU Falling Threshold
PROTECTION
S0
S0
0.725 0.74
-
- 0.70 0.715
V
V
OCSET Current Source
VTT_DDR Current Limit
VDDQ OV Level
VDDQ UV Level
VTT_DDR OV Level
VTT_DDR UV Level
VGMCH UV Level
VTT_GMCH/CPU UV Level
Thermal Shutdown Limit
IOCSET
VFB/VREF
VFB/VREF
VTT/VVREF_IN
VTT/VVREF_IN
VFB4/VREF
VFB2/VREF
TSD
By Design
S0/S3
S0/S3
S0
S0
S0
S0
By Design
18 20 22
-3.3 - 3.3
- 115 -
- 75 -
- 115 -
- 85 -
- 75 -
- 75 -
- 140 -
µA
A
%
%
%
%
%
%
°C
5 FN9142.4
February 8, 2005
5 Page 
ISL6537
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are
the small signal components which connect to sensitive
nodes or supply critical bypass current and signal coupling.
A multi-layer printed circuit board is recommended. Figure 2
shows the connections of the critical components in the
converter. Note that capacitors CIN and COUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground
plane and make all critical component ground connections
with vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminals to the output inductor short. The power
www.DataShepelat4nUe.csohmould support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
In order to dissipate heat generated by the internal VTT
LDO, the ground pad, pin 29, should be connected to the
internal ground plane through at least four vias. This allows
the heat to move away from the IC and also ties the pad to
the ground plane through a low impedance path.
The switching components should be placed close to the
ISL6537 first. Minimize the length of the connections
between the input capacitors, CIN, and the power switches
by placing them nearby. Position both the ceramic and bulk
input capacitors as close to the upper MOSFET drain as
possible. Position the output inductor and output capacitors
between the upper and lower MOSFETs and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB
pin with vias tied straight to the ground plane as required.
Feedback Compensation - PWM Buck Converter
Figure 3 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The error
amplifier output (VE/A) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the PHASE node. The
PWM wave is smoothed by the output filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR. The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage ∆VOSC.
12VATX
P12V
GNDP
5VSBY
ISL6537
UGATE
PHASE
CBP
5VDUAL
5VSBY
CBP
CIN
Q1 L1
VDDQ
LGATE
COMP
FB
VDDQ(2)
VTT(2)
Q2 COUT1
C2
R2
C1
R1
R4 C3 R3
VDDQ
VTT
COUT2
DRIVE4
FB4
DRIVE3
FB3
REFADJ4
DRIVE2
FB2
GND PAD
R5
R6
R7
R8
Q3
COUT3
Q4
VGMCH
COUT4
Q5
VTT_GMCH/CPU
COUT4
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 2. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
11 FN9142.4
February 8, 2005
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ISL6537.PDF ] | |
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