PDF ADS5272 Data sheet ( Hoja de datos )

Número de pieza	ADS5272
Descripción	65MSPS ADC
Fabricantes	Burr-Brown Corporation
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No Preview Available ! ADS5272 8-Channel, 12-Bit, 65MSPS ADC with Serial LVDS Interface SBAS324 − JUNE 2004 FEATURES D Maximum Sample Rate: 65MSPS D 12-Bit Resolution D No Missing Codes www.DataSheet4UD.comPower Dissipation: 996mW D CMOS Technology D Simultaneous Sample-and-Hold D 70.5dB SNR at 10MHz IF D Internal and External References D 3.3V Digital/Analog Supply D Serialized LVDS Outputs D Integrated Frame and Synch Patterns D MSB and LSB First Modes D Option to Double LVDS Clock Output Currents D Pin- and Format-Compatible Family D TQFP-80 PowerPAD Package APPLICATIONS D Portable Ultrasound Systems D Tape Drives D Test Equipment D Optical Networking DESCRIPTION or LSB first. The bit coinciding with the rising edge of the 1x clock output is the first bit of the word. Data is to be latched by the receiver on both the rising and falling edges of the 6x clock. The ADS5272 provides internal references, or can optionally be driven with external references. Best performance can be achieved through the internal reference mode. The device is available in a TQFP-80 PowerPAD package and is specified over a −40°C to +85°C operating range. 6X ADCLK ADCLK IN1P IN1N S/H IN2P IN2N S/H IN3P IN3N S/H IN4P IN4N S/H IN5P IN5N S/H PLL 1X ADCLK 12−Bit ADC 12−Bit ADC 12−Bit ADC 12−Bit ADC 12−Bit ADC Serializer Serializer Serializer Serializer Serializer LCLKP LCLKN ADCLKP ADCLKN OUT1P OUT1N OUT2P OUT2N OUT3P OUT3N OUT4P OUT4N OUT5P OUT5N The ADS5272 is a high-performance, 65MSPS, 8-channel, parallel analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size. An integrated phase lock loop multiplies the incoming ADC sampling clock by a factor of 12. This 12x clock is used in the process of serializing the data output from each channel. The 12x clock is also used to generate a 1x and a 6x clock, both of which are transmitted as LVDS clock outputs. The 6x clock is denoted by the differential pair LCLKP and LCLKN, while the 1x clock is denoted by ADCLKP and ADCLKN. The word output of each ADC channel can be transmitted either as MSB IN6P IN6N S/H IN7P IN7N S/H IN8P IN8N S/H 12−Bit ADC 12−Bit ADC 12−Bit ADC Serializer Serializer Serializer Reference Registers Control INT/EXT OUT6P OUT6N OUT7P OUT7N OUT8P OUT8N Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. www.ti.com Copyright  2004, Texas Instruments Incorporated 1 page ADS5272 www.ti.com SBAS324 − JUNE 2004 SWITCHING CHARACTERISTICS TMIN = −40°C, TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, −1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. ADS5272 PARAMETER SWITCHING SPECIFICATIONS tD(A) tSAMPLE Aperture Delay Aperture Jitter (uncertainty) tD(pipeline) Latency tPROP Propagation Delay CONDITIONS MIN TYP MAX UNITS 25 50 ns 2.5 ns 1 ps 6.5 cycles 5 ns www.DataSheet4US.cEomRIAL INTERFACE TIMING Data is shifted in MSB first. ADCLK Outputs change on next rising clock edge after CS goes high. CS SCLK Start Sequence t1 t2 t3 SDATA MSB t4 t5 PARAMETER t1 t2 t3 t4 t5 D6 D5 D4 DESCRIPTION Serial CLK Period Serial CLK High Time Serial CLK Low Time Minimum Data Setup Time Minimum Data Hold Time Data latched on each rising edge of SCLK. D3 D2 D1 MIN TYP 50 25 25 5 5 D0 MAX UNIT ns ns ns ns ns 5 5 Page ADS5272 www.ti.com The sampling circuit consists of a low-pass RC filter at the input to filter out noise components that might be getting differentially coupled on the input pins. The inputs are sampled on two 4pF capacitors as shown in Figure 2. The sampling on the capacitors is done with respect to an internally generated common-mode voltage (INCM). The switches connecting the sampling capacitors to the INCM are opened out first (before the switches connecting them to the analog inputs). This ensures that the charge injection arising out of the switches opening is independent of the input signal amplitude to a first-order of approximation. SP refers to a sampling clock whose falling edge comes an instant before the SAMPLE clock. The www.DataSheet4Uf.aclolimng edge of SP determines the sampling instant. 15Ω IN+ 1.5pF 15Ω IN− 1.5pF INCM (internally generated voltage) Sample 4pF SP (defines sampling instant) 1.7pF SP 4pF Sample SP INCM Figure 2. Input Circuitry INPUT OVER-VOLTAGE RECOVERY The differential full-scale input peak-to-peak supported by the ADS5272 is 2V. For a nominal value of VCM (1.5V), INP and INN can swing from 1V to 2V. The ADS5272 is specially designed to handle an over-voltage differential peak-to-peak voltage of 4V (2.5V and 0.5V swings on INP and INN). If the input common-mode is not considerably off from VCM during overload (less than 300mV), recovery from an over-voltage input condition is expected to be within 4 clock cycles. All of the amplifiers in the SHA and ADC are specially designed for excellent recovery from an overload signal. REFERENCE CIRCUIT DESIGN The digital beam-forming algorithm relies heavily on gain matching across all receiver channels. A typical system would have about 12 octal ADCs on the board. In such a case, it is critical to ensure that the gain is matched, essentially requiring the reference voltages seen by all the ADCs to be the same. Matching references within the eight channels of a chip is done by using a single internal reference voltage buffer. Trimming the reference voltages on each chip during production ensures the reference voltages are well matched across different chips. SBAS324 − JUNE 2004 All bias currents required for the internal operation of the device are set using an external resistor to ground at pin ISET. Using a 56kΩ resistor on ISET generates an internal reference current of 20µA. This current is mirrored internally to generate the bias current for the internal blocks. Using a larger external resistor at ISET reduces the reference bias current and thereby scales down the device operating power. However, it is recommended that the external resistor be within 10% of the specified value of 56k so that the internal bias margins for the various blocks are proper. Buffering the internal bandgap voltage also generates a voltage called VCM, which is set to the midlevel of REFT and REFB, and is accessible on a pin. The internal buffer driving VCM has a drive of ±2mA. It is meant as a reference voltage to derive the input common-mode in case the input is directly coupled. When using the internal reference mode, a resistor greater than 2Ω should be added between the reference pins (REFT and REFB) and the decoupling capacitor, as shown in Figure 3. ADS5272 REFT > 2Ω REFB > 2Ω 0.1µF 2.2µF 2.2µF 0.1µF Figure 3. Internal Refernce Mode The device also supports the use of external reference voltages. This mode involves forcing REFT and REFB externally. In this mode, the internal reference buffer is tri-stated. Since the switching current for the eight ADCs come from the externally forced references, it is possible for the performance to be slightly less than when the internal references are used. It should be noted that in this mode, VCM and ISET continue to be generated from the internal bandgap voltage, as in the internal reference mode. It is therefore important to ensure that the common-mode voltage of the externally forced reference voltages matches to within 50mV of VCM. CLOCKING The eight channels on the chip run off a single ADCLK input. To ensure that the aperture delay and jitter are same for all the channels, a clock tree network is used to generate individual sampling clocks to each channel. The 11 11 Page

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