PDF ADS5277 Data sheet ( Hoja de datos )

Número de pieza	ADS5277
Descripción	65MSPS Analog-to-Digital Converter
Fabricantes	Burr-Brown Corporation
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No Preview Available ! BurrĆBrown Products from Texas Instruments ADS5277 SBAS333C – FEBRUARY 2005 – REVISED SEPTEMBER 2005 8-Channel, 10-Bit, 65MSPS Analog-to-Digital Converter with Serial LVDS Interface FEATURES • Maximum Sample Rate: 65MSPS • 10-Bit Resolution • No Missing Codes • Total Power Dissipation: Internal Reference: 911mW External Reference: 845mW • CMOS Technology • Simultaneous Sample-and-Hold • 61.7dBFS SNR at 5MHz IF • 3.3V Digital/Analog Supply • Serialized LVDS Outputs • Integrated Frame and Bit Patterns • Option to Double LVDS Clock Output Currents • Four Current Modes for LVDS • Pin- and Format-Compatible Family • TQFP-80 PowerPAD™ Package APPLICATIONS • Portable Ultrasound Systems • Tape Drives • Test Equipment DESCRIPTION The ADS5277 is a high-performance, CMOS, 65MSPS, 8-channel analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size. MODEL ADS5270 ADS5271 ADS5272 ADS5273 RELATED PRODUCTS RESOLUTION (BITS) 12 12 12 12 SAMPLE RATE (MSPS) 40 50 65 70 CHANNELS 8 8 8 8 An integrated phase lock loop (PLL) multiplies the incoming ADC sampling clock by a factor of 12. This high-frequency clock is used in the data serialization and transmission process. The word output of each internal ADC is serialized and transmitted either MSB or LSB first. The word consists of 12 bits, of which the 2 LSBs are zeroes and the remaining 10 bits correspond to the output from the ADC. This formatting is done in order to keep the interface compatible with the 12-bit parts of the family. In addition to the eight data outputs, a bit clock and a word clock are also transmitted. The bit clock is at 6x the speed of the sampling clock, whereas the word clock is at the same speed of the sampling clock. The ADS5277 provides internal references, or can optionally be driven with external references. Best performance is achieved through the internal reference mode. The ADS5277 is available in a PowerPAD TQFP-80 package and is specified over a –40°C to +85°C operating range. ADCLK 6x ADCLK 12x ADCLK PLL 1x ADCLK I N1 P IN1N S/H I N2 P IN2N S/H I N3 P IN3N S/H I N4 P IN4N S/H I N5 P IN5N S/H I N6 P IN6N S/H I N7 P IN7N S/H I N8 P IN8N S/H 10−Bit ADC 10−Bit ADC 10−Bit ADC 10−Bit ADC 10−Bit ADC 10−Bit ADC 10−Bit ADC 10−Bit ADC Se riali ze r Se riali ze r Se riali ze r Se riali ze r Se riali ze r Se riali ze r Se riali ze r Se riali ze r Reference Registers Control I NT /E X T LCLKP LCLKN ADCLKP ADCLKN OUT1P OUT1N OUT2P OUT2N OUT3P OUT3N OUT4P OUT4N OUT5P OUT5N OUT6P OUT6N OUT7P OUT7N OUT8P OUT8N Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated 1 page ADS5277 www.ti.com SBAS333C – FEBRUARY 2005 – REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, sampling rate = 65MSPS, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. All values are applicable after the device has been reset. PARAMETER ANALOG INPUT Differential Input Capacitance Analog Input Common-Mode Range Differential Full-Scale Input Voltage Range Voltage Overload Recovery Time(7) Input Bandwidth DIGITAL INPUTS VIH High Level Input Voltage VIL Low Level Input Voltage CIN Input Capacitance DIGITAL DATA OUTPUTS Data Format Data Bit Rate SERIAL INTERFACE SCLK Serial Clock Input Frequency TEST CONDITIONS Internal Reference External Reference –3dBFS, 25Ω Series Resistances ADS5277 MIN TYP MAX UNITS 4.0 VCM ± 50 2.03 2.03 × (VREFT – VREFB) 3.0 300 pF mV VPP VPP CLK Cycles MHz 2.2 0.6 3 Straight Offset Binary 240 780 20 V V pF Mbps MHz (7) A differential ON/OFF pulse is applied to the ADC input. The differential amplitude of the pulse in its ON (high) state is twice the full-scale range of the ADC, while the differential amplitude of the pulse in its OFF (low) state is zero. The overload recovery time of the ADC is measured as the time required by the ADC output code to settle within 1% of full-scale, as measured from its mid-code value when the pulse is switched from ON (high) to OFF (low). REFERENCE SELECTION MODE Internal Reference; FSR = 2.03VPP External Reference; FSR = 2.03 × (VREFT – VREFB) INT/EXT 1 0 DESCRIPTION Default with internal pull-up. Internal reference is powered down. The common-mode voltage of the external reference should be within 50mV of VCM. VCM is derived from the internal bandgap voltage. 5 5 Page www.ti.com Top View ADS5277 SBAS333C – FEBRUARY 2005 – REVISED SEPTEMBER 2005 PIN CONFIGURATION HTQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AVDD 1 IN1P 2 IN1N 3 AVSS 4 IN2P 5 IN2N 6 AVDD 7 AVSS 8 IN3P 9 IN3N 10 AVSS 11 IN4P 12 IN4N 13 AVDD 14 LVSS 15 PD 16 LVSS 17 LVSS 18 LCLKP 19 LCLKN 20 ADS5277 60 AVDD 59 IN8N 58 IN8P 57 AVSS 56 IN7N 55 IN7P 54 AVDD 53 AVSS 52 IN6N 51 IN6P 50 AVSS 49 IN5N 48 IN5P 47 AVDD 46 LVSS 45 RESET 44 LVSS 43 LVSS 42 ADCLKN 41 ADCLKP 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 11 11 Page

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