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PDF MPC9447 Data sheet ( Hoja de datos )
| Número de pieza | MPC9447 | |
| Descripción | 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer | |
| Fabricantes | IDT | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MPC9447 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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MOTOROLA
SEMICONDUCTOR
TECHNFICreALesDcATaAle
Semiconductor,
Inc.
Order Number: MPC9447/D
DAReTvA2, 0S4H/20E03ET
3.3V/2.5V 1:9 LVCMOS Clock Fanout
Bu3ff.e3r V/2.5V 1:9 LVCMOS Clock
MPC9447
The MPC9447 is a 3.3V or 2.5V compatible, 1:9 clock fanout buffer
targeted for high performance clock tree applications. With output
frequencies up to 350 MHz and output skews less than 150 ps, the device
meets the needs of most demanding clock applications.
www.DataSheeFte4Uat.cuormes
• 9 LVCMOS Compatible Clock Outputs
• 2 Selectable, LVCMOS Compatible Inputs
• Maximum Clock Frequency of 350 MHz
• Maximum Clock Skew of 150 ps
• Synchronous Output Stop in Logic Low State Eliminates Output Runt
Pulses
• High--Impedance Output Control
• 3.3V or 2.5V Power Supply
• Drives up to 18 Series Terminated Clock Lines
• Ambient Temperature Range --40_C to +85_C
• 32 Lead LQFP Packaging
• Supports Clock Distribution in Networking, Telecommunications, and
Computer Applications
• Pin and Function Compatible to MPC947
3.3 V/2.5 V LVCMOS 1:9
CLOCK FANOUT BUFFER
FA SUFFIX
32--LEAD LQFP PACKAGE
CASE 873A
Functional Description
MPC9447 is specifically designed to distribute LVCMOS compatible
clock signals up to a frequency of 350 MHz. Each output provides a
precise copy of the input signal with a near zero skew. The outputs buffers
support driving of 50Ω terminated transmission lines on the incident
edge: each is capable of driving either one parallel terminated or two
series terminated transmission lines.
Two selectable independent LVCMOS compatible clock inputs are available, providing support of redundant clock source
systems. The MPC9447 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the
output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force the
outputs into high--impedance mode.
All inputs have an internal pull--up or pull--down resistor preventing unused and open inputs from floating. The device supports
a 2.5V or 3.3V power supply and an ambient temperature range of --40_C to +85_C. The MPC9447 is pin and function compatible
but performance--enhanced to the MPC947.
IDT™ 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
1
MPC9447
1 page  
MPC9447
3.3V/2.5V 1:9 LVCMOS Clock FanoutFBrueffeer scale Semiconductor, Inc.
MPC94N4E7TCOM
APPLICATION INFORMATION
Figure 3. Output Clock Stop (CLK_STOP) Timing
Diagram
CCLK0 or
CCLK1
CLK_STOP
Q0 to Q8
www.DataSheet4DUri.TcvhoinemgMTPraCn9s4m47issciloonckLdinrievser was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of 17Ω (VCC=3.3V), the
outputs can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to Motorola application note
AN1091. In most high performance clock networks,
point--to--point distribution of signals is the method of choice.
In a point--to--point scheme, either series terminated or
parallel terminated transmission lines can be used. The
parallel technique terminates the signal at the end of the line
with a 50Ω resistance to VCC÷2.
MPC9447
OUTPUT
BUFFER
IN 17Ω
MPC9447
OUTPUT
BUFFER
IN 17Ω
RS = 33Ω
ZO = 50Ω
RS = 33Ω
ZO = 50Ω
RS = 33Ω
ZO = 50Ω
OutA
OutB0
OutB1
Figure 4. Single versus Dual Transmission Lines
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9447 clock driver. For the series
terminated case, however, there is no DC current draw; thus,
the outputs can drive multiple series terminated lines.
Figure 4 “Single versus Dual Transmission Lines” illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme,
the fanout of the MPC9447 clock driver is effectively doubled
due to its capability to drive multiple lines at VCC=3.3V.
3.0
OutA
2.5 tD = 3.8956
2.0
In
1.5
OutB
tD = 3.9386
1.0
0.5
0
2 4 6 8 10 12 14
TIME (nS)
Figure 5. Single versus Dual Line Termination
Waveforms
The waveform plots in Figure 5 “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases,
the drive capability of the MPC9447 output buffer is more
than sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations
a delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output--to--output skew
of the MPC9447. The output waveform in Figure 5 “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform; this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 33Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50Ω || 50Ω
RS = 33Ω || 33Ω
R0 = 17Ω
VL = 3.0 ( 25 ÷ (16.5+17+25)
= 1.28V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.5V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
Since this step is well above the threshold region it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines, the
situation in Figure 6 “Optimized Dual Line Termination”
should be used. In this case, the series terminating resistors
IDT™ 3T.3IMVI/N2.G5VSO1:L9ULTVIOCNMSOS Clock Fanout Buffer
5
Freescale Timing Solutions Organization has bFeoenr aMcqourireedInbyfoInrtmegaratteiodnDeOvinceTThecihsnoPlorogyd,uIncct,
Go to: www5.freescale.com
MOTOROLAMPC9447
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MPC9447.PDF ] | |
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