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PDF APW7066 Data sheet ( Hoja de datos )
| Número de pieza | APW7066 | |
| Descripción | Dual Synchronous Buck PWM Controllers and One Linear Controller | |
| Fabricantes | Anpec Electronics Coropration | |
| Logotipo |  |
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APW7066
Dual Synchronous Buck PWM Controllers and One Linear Controller
Features
• Two Synchronous Buck Converters and A
Linear Regulator
• VIN Range up to 12V
• Input Power Supplies Require 12V and 5V or
Use 12V to Generate a Shunt Regulator 5.8V
• 0.6V Reference for VOUT1 and VOUT3
with 0.8% Accurate
• 3.3V Reference for VOUT2 with 0.8% Accurate
• Buffered VTT Reference Output
• Three Outputs have Independent Soft-Start
and Enable
• Internal 300kHz Oscillator and Programmable
Frequency Range from 70 kHz to 800kHz
• Synchronous Switching Frequency
• DDR Mode or Independent Mode Selection
• Phase Shift Selection
• Power Good Function
• Short-Circuit Protection for VOUT1 and VOUT2
• Thermally Enhanced TSSOP-24P and
QFN5x5-32 Packages
• Lead Free and Green Devices Available
(RoHS Compliant)
Applications
• Graphic Cards
• DDR memory Power Supplies
• Low-Voltage Distributed Power Supplies
General Description
The APW7066 has two synchronous buck PWM control-
lers and one linear controller with high precision internal
references voltage to offer accurate outputs. The PWM
controllers are designed to drive two N-channel MOSFETs
in synchronous buck topology, and the linear controller
drives an external N-channel MOSFET. The device re-
quires 12V and 5V power supplies, if the 5V supply is not
available, VCC12 can offer an optional shunt regulator
5.8V for 5V supply.
All outputs have independent soft-start and enable func-
tions by SS/EN pins to control. Connect a capacitor from
each SS/EN pin to the ground for setting the soft-start
time, and pulling the SS/EN pin below 1V to disable
regulator. Pull the SS2/EN2 to VCC, enter the DDR mode,
the SS1/EN1 controls both VOUT1 and VOUT2, and al-
lows VOUT2 to track VOUT1. It also offers the phase shift
function by REFOUT pin to select the phase shift between
VOUT1 and VOUT2 in DDR mode or Independent mode.
When all SS/EN pins exceed 3.3V and no faults are
detected, the PGOOD pin goes high to indicate the regu-
lators are ready. If any of the SS/EN pins goes below 3.2V
or any of the outputs has a fault condition, the PGOOD pin
will be pulled low.
The internal oscillator is nominally 300kHz (keep the FS/
SYNC pin open or short to GND), and it offers the pro-
grammable frequency function from 70kHz to 800kHz; con-
necting a resistor from FS/SYNC to VCC12 to decrease
the frequency, conversely, connect a resistor from FS/
SYNC to GND to increase the frequency.The IC also pro-
vides the synchronous frequency function. Connect the
LGATE signal of another converter to FS/SYNC pin; forc-
ing the switching frequency to follow the external clock.
The possible synchronous frequency is from 150kHz to
800kHz. There is no R sensing or under-voltage sens-
ds(on)
ing on APW7066. However, it provides a simple short-
circuit protection by monitoring the COMP1 and COMP2
for over-voltage. When any of two pins exceeds their trip
point and the condition persists for 1-2 internal clock cycle
(3-6µs at 300kHz), then it will shut down all regulators.
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.8 - Aug., 2009
1
www.anpec.com.tw
1 page  
APW7066
Electrical Characteristics (Cont.)
Operating Conditions: VCC = 5V, VCC12 = 12V, TA = 0 to 70°C, unless Otherwise Specified.
Symbol
Parameter
Test Conditions
APW7066
Min. Typ. Max.
VREF
Output Voltage
Output Accuracy
1.1µF max capacitance
- 3.3 -
-0.8 - +0.8
Source Current
- - 2.0
REFOUT (VTTREF)
Output Voltage
Determined by REFIN voltage
0.6 - 3.3
Offset Voltage
-10 - +10
Source Current
0.2 - 20
Sink Current
- - 0.48
Output Capacitance
- 0.1 -
Output High Voltage Minimum
To select 0 degree phase; see Table 1 - 3.8 VCC
ENABLE/SOFTSTART (SS/EN 1,2,3)
Enable Threshold
EN Rising
- 1.05 -
EN falling
- 0.95 -
Soft-Start Current
- -30 -
Soft-Start High Voltage
End of ramp
- 3.5 -
Output High Voltage
To select DDR mod; see Table 1
- 3.8 VCC
FS/SYNC PLL
Frequency range of Lock-in
150 - 800
High Voltage
From LG pin of another IC, for example -
- 12
GATE DRIVERS
Output1 GATE Driver Source
UGATE1, LGATE1=3V, BOOT=12V
- 1.8 -
Output2 GATE Driver Source
UGATE2, LGATE2=3V, BOOT=12V
-1-
Output1 GATE Driver Sink
UGATE1, LGATE1=3V, BOOT=12V
- 2.5 -
Output2 GATE Driver Sink
UGATE2, UGATE2=3V, BOOT=12V
-4-
Output Voltage
UGATE1, UGATE2
- - 30
Output Voltage
LGATE1, LGATE2
- 12 -
Unit
V
%
mA
V
mV
mA
mA
µF
V
V
µA
V
V
kHz
V
A
A
Ω
Ω
V
V
Copyright © ANPEC Electronics Corp.
Rev. A.8 - Aug., 2009
5
www.anpec.com.tw
5 Page 
APW7066
Typical Operating Characteristics (Cont.)
UG2 Falling
UG2 (10V/div)
Phase2 (10V/div)
LG2 (10V/div)
Time(50ns/div)
PGOOD Sink Current vs. PGOOD Voltage
3
2.5
2
1.5
1
0.5
0
0 10 20 30 40
PGOOD Voltage (mV)
REFOUT Voltage vs. Source Current
3.35
3.34
3.33
3.32
3.31
3.3
3.29
3.28
3.27
3.26
3.25
0
5 10 15
Source Current (mA)
20
VREF Voltage vs. Source Current
3.32
3.31
3.3
3.29
3.28
0
0.5 1
1.5
Source Current (mA)
2
Copyright © ANPEC Electronics Corp.
Rev. A.8 - Aug., 2009
11
www.anpec.com.tw
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet APW7066.PDF ] | |
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