|
|
PDF HT48R52 Data sheet ( Hoja de datos )
| Número de pieza | HT48R52 | |
| Descripción | (HT48R52 / HT48R53) I/O Type 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HT48R52 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
HT48R52/HT48R53
I/O Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0002E Reading Larger than Usual MCU Tables
- HA0007E Using the MCU Look Up Table Instructions
- HA0011E HT48 & HT46 Keyboard Scan Program
- HA0019E Using the Watchdog Timer in the HT48 MCU Series
- HA0020E Using the Timer/Event Counter in the HT48 MCU Series
www.DataSheet4U.com
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· Program memory:
HT48R52: 2k´14
HT48R53: 4k´15
· 88´8 data memory
· 40 bidirectional I/O lines
· One External interrupt input
· One Internal interrupt
· 8 bit programmable timer/event counter
· 4-level subroutine nesting
· Watchdog Timer (WDT)
· Buzzer output
· Low voltage reset (LVR)
General Description
These devices are 8-bit high performance, RISC archi-
tecture microcontroller specifically designed for multiple
I/O control product applications. The advantages of low
power consumption, I/O flexibility, timer functions, oscil-
lator options, HALT and wake-up functions, watchdog
· External RC and 32768Hz crystal oscillator
· Dual clock system offers three operating modes
- Normal mode: Both RC and 32768Hz clock active
- Slow mode: 32768Hz clock only
- Idle mode: Periodical wake-up by watchdog timer
overflow
· HALT function and wake-up feature reduce power
consumption
· 14-bit table read instructions for HT48R52
· 15-bit table read instructions for HT48R53
· 63 powerful instructions
· One instruction cycle: 4 system clock periods
· All instructions in 1 or 2 instruction cycles
· Bit manipulation instructions
· Up to 0.5ms instruction cycle with 8MHz system clock
· 52-pin QFP package
timer, buzzer driver, as well as low cost, enhance the
versatility of these devices to suit a wide range of appli-
cation possibilities such as industrial control, consumer
products, subsystem controllers, etc.
Rev. 1.20
1 December 6, 2005
1 page  
HT48R52/HT48R53
www.DataSheet4U.com
A.C. Characteristics
Symbol
Parameter
Test Conditions
VDD Conditions
fSYS System Clock (RC OSC)
¾ 2.2V~5.5V
¾ 3.3V~5.5V
fTIMER Timer I/P Frequency
¾ 2.2V~5.5V
¾ 3.3V~5.5V
tWDTOSC Watchdog Oscillator Period
3V
5V
¾
¾
tFSP1
fSP Time-out Period Clock Source
from WDT
3V
With prescaler (fS/4096)
5V
tFSP2
fSP Time-out Period Clock Source
from RTC OSC
3V
With prescaler (fS/4096)
5V
tRES External Reset Low Pulse Width ¾
¾
tSST System Start-up Timer Period
¾
Power-up or wake-up
from HALT
tINT Interrupt Pulse Width
¾¾
Note: *tSYS= 1/fSYS
Min.
400
400
0
0
45
32
184
131
¾
¾
1
¾
1
Typ.
¾
¾
¾
¾
90
65
369
266
125
125
¾
1024
¾
Ta=25°C
Max. Unit
4000
8000
4000
8000
180
130
737
532
¾
¾
¾
kHz
kHz
kHz
kHz
ms
ms
ms
ms
ms
ms
ms
¾ *tSYS
¾ ms
Rev. 1.20
5 December 6, 2005
5 Page 
HT48R52/HT48R53
S y s te m C lo c k /4
32768H z
W DT O SC
O p tio n
S e le c t
fS
4 - B it D iv id e r
8 - S ta g e P r e s c a le r
P S C 2~P S C 0
8 -to -1 M U X
Watchdog Timer
9 - B it C o u n te r
W D T T im e - o u t
www.DataSheet4U.com
Watchdog Timer - WDT
The WDT clock source is implemented by a WDT OSC,
external 32768Hz (fRTC) or an instruction clock (system
clock divided by 4), determined by option. This timer is
designed to prevent a software malfunction or sequence
from jumping to an unknown location with unpredictable
results. The Watchdog can be disabled by option. If the
Watchdog Timer is disabled, all the execution related to
WDT results in no operation.
If the device operates in a noisy environment, using the
on-chip WDT OSC or 32768Hz crystal oscillator is
strongly recommended.
When the WDT clock source is selected, it will be first di-
vided by 16 (4-stage), and then divided by TMRC
prescaler (8-stage), after that, divided by 512 (9-stage)
to get the nominal time-out period. By using the TMRC
prescaler, longer time-out periods can be realized. Writ-
ing data to PSC2, PSC1, PSC0 can give different
time-out periods. The WDT OSC period is 65ms. This
time-out period may vary with temperature, VDD and
process variations. The WDT OSC always works for any
operation mode.
If the instruction clock (system clock/4) is selected as
the WDT clock source, the WDT operates in the same
manner.
If the WDT clock source is the 32768Hz, the WDT also
operates in the same manner.
The WDT time-out under normal mode or slow mode will
initialize a ²chip reset² and set the status bit ²TO². But in
the idle mode (HALT instruction is executed) the
time-out will initialize a ²warm reset² and only the pro-
gram counter and stack pointer are reset to 0.
To clear the WDT contents (not including the 4-bit di-
vider and the 8-stage prescaler), three methods are
adopted; external reset (a low level to RES pin), soft-
ware instruction and a ²HALT² instruction.
The software instruction include ²CLR WDT² and the
other set ²CLR WDT1² and ²CLR WDT2². Of these two
types of instruction, only one can be active depending
on the mask option ²WDT² instruction. If the ²CLR
WDT² is selected (i.e. One clear instruction), any execu-
tion of the CLR WDT instruction will clear the WDT. In
the case that ²CLR WDT1² and ²CLR WDT2² are cho-
sen (i.e. two clear instructions), these two instructions
must be executed to clear the WDT; otherwise, the WDT
may reset the chip as a result of time-out.
Buzzer Output
The PB0 and PB1 are pin-shared with BZ and BZ signal,
respectively. If the BZ & BZ option is selected, the output
signal in output mode of PB0/PB1 will be the generated
buzzer signal . The input mode always remain in its orig-
inal functions. Once the BZ & BZ option is selected, the
buzzer output signals are controlled by the PB0 data
register only. The I/O functions of PB0/PB1 are shown
below.
PBC Register
PBC.0
PBC Register PB data Register PB data Register
PBC.1
PB.0
PB.1
001X
000X
011X
010X
1 0XD
1 1XX
PB0/PB1 Pin Function Control
Note: ²X² stands for don¢t care
²D² stands for data ²0² or ²1²
Output Function
PB0=BZ, PB1=BZ
PB0=0, PB1=0
PB0=BZ, PB1=Input
PB0=0, PB1=Input
PB0=Input, PB1=D
PB0=Input, PB1=Input
Rev. 1.20
11 December 6, 2005
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT48R52.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HT48R50 | (HT48Rxx) 8-Bit Microcontroller Series | Holtek Semiconductor |
| HT48R50-1 | 8-bit OTP Microcontrollers |  Holtek Semiconductor Inc |
| HT48R50-2 | 8-bit OTP Microcontrollers | Holtek Semiconductor Inc |
| HT48R502 | I/O Type 8-Bit OTP MCU | Holtek Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |