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PDF LM75A Data sheet ( Hoja de datos )
| Número de pieza | LM75A | |
| Descripción | Digital temperature sensor and thermal Watchdog | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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LM75A
Digital temperature sensor and thermal watchdog
Rev. 04 — 10 July 2007
Product data sheet
1. General description
The LM75A is a temperature-to-digital converter using an on-chip band gap temperature
sensor and Sigma-delta A-to-D conversion technique. The device is also a thermal
detector providing an overtemperature detection output. The LM75A contains a number of
data registers: Configuration register (Conf) to store the device settings such as device
operation mode, OS operation mode, OS polarity and OS fault queue as described in
Section 7 “Functional description”; temperature register (Temp) to store the digital temp
reading, and set-point registers (Tos and Thyst) to store programmable overtemperature
shutdown and hysteresis limits, that can be communicated by a controller via the 2-wire
serial I2C-bus interface. The device also includes an open-drain output (OS) which
becomes active when the temperature exceeds the programmed limits. There are three
selectable logic address pins so that eight devices can be connected on the same bus
without address conflict.
The LM75A can be configured for different operation conditions. It can be set in normal
mode to periodically monitor the ambient temperature, or in shutdown mode to minimize
power consumption. The OS output operates in either of two selectable modes:
OS comparator mode or OS interrupt mode. Its active state can be selected as either
HIGH or LOW. The fault queue that defines the number of consecutive faults in order to
activate the OS output is programmable as well as the set-point limits.
The temperature register always stores an 11-bit 2's complement data giving a
temperature resolution of 0.125 °C. This high temperature resolution is particularly useful
in applications of measuring precisely the thermal drift or runaway.
The device is powered-up in normal operation mode with the OS in comparator mode,
temperature threshold of 80 °C and hysteresis of 75 °C, so that it can be used as a
stand-alone thermostat with those pre-defined temperature set points.
2. Features
I Pin-for-pin replacement for industry standard LM75 and offers improved temperature
resolution of 0.125 °C and specification of a single part over power supply range from
2.8 V to 5.5 V
I Small 8-pin package types: SO8 and TSSOP8
I I2C-bus interface with up to 8 devices on the same bus
I Power supply range from 2.8 V to 5.5 V
I Temperatures range from −55 °C to +125 °C
I 11-bit ADC that offers a temperature resolution of 0.125 °C
1 page  
NXP Semiconductors
LM75A
Digital temperature sensor and thermal watchdog
In both cases, comparator mode and interrupt mode, the OS output is activated only if a
number of consecutive faults, defined by the device fault queue, has been met. The fault
queue is programmable and stored in the two bits, B3 and B4, of the Configuration
register. Also, the OS output active state is selectable as HIGH or LOW by setting
accordingly the configuration register bit B2.
At power-up, the device is put into normal operation mode, the Tos is set to 80 °C, the Thyst
is set to 75 °C, the OS active state is selected LOW and the fault queue is equal to 1. The
temp reading data is not available until the first conversion is completed in about 100 ms.
The OS response to the temperature is illustrated in Figure 4.
Tos
Thyst
OS reset
OS active
reading temperature limits
OS output in comparator mode
OS reset
OS active
(1) (1)
OS output in interrupt mode
(1)
002aad032
(1) OS is reset by either reading register. It is assumed that the fault queue is met at each Tos and
Thyst crossing point.
Fig 4. OS response to temperature
7.2 I2C-bus serial interface
The LM75A can be connected to a compatible 2-wire serial interface I2C-bus as a slave
device under the control of a controller or master device, using two device terminals, SCL
and SDA. The controller must provide the SCL clock signal and write/read data to/from the
device through the SDA terminal. Notice that if the I2C-bus common pull-up resistors have
not been installed as required for I2C-bus, then an external pull-up resistor, about 10 kΩ,
is needed for each of these two terminals. The bus communication protocols are
described in Section 7.10.
7.3 Slave address
The LM75A slave address on the I2C-bus is partially defined by the logic applied to the
device address pins A2, A1 and A0. Each of them is typically connected either to GND for
logic 0, or to VCC for logic 1. These pins represent the three LSB bits of the device 7-bit
address. The other four MSB bits of the address data are preset to ‘1001’ by hard wiring
inside the LM75A. Table 4 shows the device’s complete address and indicates that up to
LM75A_4
Product data sheet
Rev. 04 — 10 July 2007
© NXP B.V. 2007. All rights reserved.
5 of 24
5 Page 
NXP Semiconductors
LM75A
Digital temperature sensor and thermal watchdog
When the power supply voltage is dropped below the device power-on reset level of
approximately 1.9 V (POR) and then rises up again, the device will be reset to its default
condition as listed above.
7.10 Protocols for writing and reading the registers
The communication between the host and the LM75A must strictly follow the rules as
defined by the I2C-bus management. The protocols for LM75A register read/write
operations are illustrated in Figure 5 to Figure 10 together with the following definitions:
1. Before a communication, the I2C-bus must be free or not busy. It means that the SCL
and SDA lines must both be released by all devices on the bus, and they become
HIGH by the bus pull-up resistors.
2. The host must provide SCL clock pulses necessary for the communication. Data is
transferred in a sequence of 9 SCL clock pulses for every 8-bit data byte followed by
1-bit status of the acknowledgement.
3. During data transfer, except the START and STOP signals, the SDA signal must be
stable while the SCL signal is HIGH. It means that the SDA signal can be changed
only during the LOW duration of the SCL line.
4. S: START signal, initiated by the host to start a communication, the SDA goes from
HIGH to LOW while the SCL is HIGH.
5. RS: RE-START signal, same as the START signal, to start a read command that
follows a write command.
6. P: STOP signal, generated by the host to stop a communication, the SDA goes from
LOW to HIGH while the SCL is HIGH. The bus becomes free thereafter.
7. W: write bit, when the write/read bit = LOW in a write command.
8. R: read bit, when the write/read bit = HIGH in a read command.
9. A: device acknowledge bit, returned by the LM75A. It is LOW if the device works
properly and HIGH if not. The host must release the SDA line during this period in
order to give the device the control on the SDA line.
10. A’: master acknowledge bit, not returned by the device, but set by the master or host
in reading 2-byte data. During this clock period, the host must set the SDA line to
LOW in order to notify the device that the first byte has been read for the device to
provide the second byte onto the bus.
11. NA: Not Acknowledge bit. During this clock period, both the device and host release
the SDA line at the end of a data transfer, the host is then enabled to generate the
STOP signal.
12. In a write protocol, data is sent from the host to the device and the host controls the
SDA line, except during the clock period when the device sends the device
acknowledgement signal to the bus.
13. In a read protocol, data is sent to the bus by the device and the host must release the
SDA line during the time that the device is providing data onto the bus and controlling
the SDA line, except during the clock period when the master sends the master
acknowledgement signal to the bus.
LM75A_4
Product data sheet
Rev. 04 — 10 July 2007
© NXP B.V. 2007. All rights reserved.
11 of 24
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