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PDF MAX9424 Data sheet ( Hoja de datos )
| Número de pieza | MAX9424 | |
| Descripción | (MAX9424 - MAX9427) Lowest Jitter Quad PECL-to-ECL Differential Translators | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-2390; Rev 0; 4/02
Lowest Jitter Quad PECL-to-ECL
Differential Translators
General Description
The MAX9424–MAX9427 high-speed, low-skew quad
PECL-to-ECL translators are designed for high-speed
data and clock driver applications. These devices feature
an ultra-low 0.24ps(RMS) random jitter and channel-to-
channel skew is less than 90ps in asynchronous mode.
The four channels can be operated synchronously with
an external clock, or in asynchronous mode determined
by the state of the SEL input. An enable input provides
the ability to force all the outputs to a differential low state.
The parts differ from one another by their input and out-
put termination options. The input options are an open
input or an internal differential 100Ω termination. The
output options are an open-emitter output or a series
50Ω termination. See Ordering Information.
The MAX9424–MAX9427 operate from a positive voltage
supply of +2.375V to +5.5V, and a negative supply volt-
age of -2.375V to -5.5V and operate across the extended
temperature range of -40°C to +85°C. They are offered in
32-pin 5mm x 5mm TQFP and space-saving 5mm x 5mm
QFN packages.
Applications
Data and Clock Driver and Buffer
Central Office Backplane Clock Distribution
DSLAM Backplane
Base Station
ATE
TOP VIEW
Features
o 0.24ps RMS Added Random Jitter
o 10ps Channel-to-Channel Skew in Synchronous
Mode
o Guaranteed 500mV Differential Output at 3GHz
Clock Frequency
o 420ps Propagation Delay in Asynchronous Mode
o Functionally Compatible with
SK4426 (MAX9424)
SK4430 (MAX9425)
SK4436 (MAX9426)
SK4440 (MAX9427)
o Integrated 50Ω Outputs (MAX9425/MAX9427)
o Integrated 100Ω Inputs (MAX9426/MAX9427)
o Synchronous/Asynchronous Operation
Ordering Information
PART
TEMP
RANGE
PIN-
PACKAGE
INPUT
(IN_,
IN_)
OUTPUT
(OUT_,
OUT_)
MAX9424EHJ -40°C to +85°C 32 TQFP Open Open
MAX9424EGJ* -40°C to +85°C 32 QFN Open Open
MAX9425EHJ -40°C to +85°C 32 TQFP Open 50Ω
MAX9425EGJ* -40°C to +85°C 32 QFN Open 50Ω
MAX9426EHJ -40°C to +85°C 32 TQFP 100Ω Open
MAX9426EGJ* -40°C to +85°C 32 QFN 100Ω Open
MAX9427EHJ -40°C to +85°C 32 TQFP 100Ω 50Ω
MAX9427EGJ* -40°C to +85°C 32 QFN 100Ω 50Ω
*Future product—contact factory for availability.
Pin Configurations
TOP VIEW
VCC 1
SEL 2
SEL 3
CLK 4
CLK 5
EN 6
EN 7
VCC 8
32 31 30 29 28 27 26 25
MAX9424
MAX9425
MAX9426
MAX9427
24 VGG
23 OUT1
22 OUT1
21 VEE
20 VEE
19 OUT2
18 OUT2
17 VGG
9 10 11 12 13 14 15 16
*
VCC 1
SEL 2
SEL 3
CLK 4
CLK 5
EN 6
EN 7
VCC 8
*
MAX9424
MAX9425
MAX9426
MAX9427
*
24 VGG
23 OUT1
22 OUT1
21 VEE
20 VEE
19 OUT2
18 OUT2
17 VGG
*
TQFP (5mm x 5mm)
QFN
NOTE: CORNER PINS ARE CONNECTED TO VGG.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
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PIN
1, 8
2
3
4
5
6
7
9
10
11, 17, 24,
30
12
13
14, 20, 21,
27
15
16
18
19
22
23
25
26
28
29
31
32
Lowest Jitter Quad PECL-to-ECL
Differential Translators
NAME
VCC
SEL
SEL
CLK
CLK
EN
EN
IN3
IN3
VGG
OUT3
OUT3
VEE
IN2
IN2
OUT2
OUT2
OUT1
OUT1
IN1
IN1
OUT0
OUT0
IN0
IN0
Pin Description
FUNCTION
Positive Supply Voltage. Bypass VCC to VGG with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
Noninverting Differential Select Input. Setting SEL = 1 and SEL = 0 enables all four channels to
operate independently. Setting SEL = 0 and SEL = 1 enables all four channels to be synchronized to
CLK.
Inverting Differential Select Input
Noninverting Differential Clock Input
Inverting Differential Clock Input
Noninverting Differential Output Enable Input. Setting EN = 1 and EN = 0 enables all four outputs.
Setting EN = 0 and EN = 1 disables all four outputs.
Inverting Differential Output Enable Input
Noninverting Differential Input 3
Inverting Differential Input 3
Ground Reference
Inverting Differential Output 3
Noninverting Differential Output 3
Negative Supply Voltage. Bypass from VEE to VGG with 0.1µF and 0.01µF ceramic capacitors. Place
the capacitors as close to the device as possible with the smaller value capacitor closest to the
device.
Noninverting Differential Input 2
Inverting Differential Input 2
Inverting Differential Output 2
Noninverting Differential Output 2
Noninverting Differential Output 1
Inverting Differential Output 1
Inverting Differential Input 1
Noninverting Differential Input 1
Noninverting Differential Output 0
Inverting Differential Output 0
Inverting Differential Input 0
Noninverting Differential Input 0
_______________________________________________________________________________________ 5
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Lowest Jitter Quad PECL-to-ECL
Differential Translators
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet MAX9424.PDF ] | |
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