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PDF MT29F1G08ABB Data sheet ( Hoja de datos )
| Número de pieza | MT29F1G08ABB | |
| Descripción | (MT29F1GxxABB) 1Gb NAND Flash Memory | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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Micron Confidential and Proprietary
Advance‡
1Gb: x8, x16 NAND Flash Memory
Features
1Gb NAND Flash Memory
MT29F1GxxABB
For the latest data sheet, refer to Micron's Web site: www.micron.com/datasheets
Features
• Organization
• Page size x8: 2,112 bytes (2,048 + 64 bytes)
• Page size x16: 1,056 words (1,024 + 32 words)
• Block size: 64 pages (128K + 4K bytes)
• Device size: 1Gb: 1,024 blocks
• READ performance
• Random READ: 25µs (MAX)
• Sequential READ: 50ns (MIN)
• WRITE performance
• PROGRAM PAGE: 300µs (TYP)
• BLOCK ERASE: 2.0ms (TYP)
• Endurance: 100,000 PROGRAM/ERASE cycles
• Data retention: 10 years
• The first block (block address 00h) is guaranteed to
be valid without ECC (up to 1,000 PROGRAM/ERASE
cycles).
• VCC: 1.65V–1.95V
• Automated PROGRAM and ERASE
• Basic NAND Flash command set
• PAGE READ, RANDOM DATA READ, READ ID,
READ STATUS, PROGRAM PAGE, RANDOM
DATA INPUT, PROGRAM PAGE CACHE MODE,
INTERNAL DATA MOVE, INTERNAL DATA MOVE
with RANDOM DATA INPUT, BLOCK ERASE,
RESET
• New commands
• PAGE READ CACHE MODE
• READ ID2 (contact factory)
• READ UNIQUE ID (contact factory)
• Programmable I/O
• OTP
• BLOCK LOCK
• Operation status byte: Provides a software method
for detecting:
• Operation completion
• Pass/fail condition
• Write-protect status
• Ready/busy# pin (R/B#)
• Provides a hardware method of detecting
operation completion
• LOCK signal: Protects selectable ranges of blocks
• WP# signal: Write-protects the entire device
Figure 1: 63-Ball VFBGA x8
Options1
• Configuration
• x8
• x16
• Package
• 63-ball VFBGA
13mm x 10.5mm x 1.0mm
• Operating temperature
• Commercial temperature (0 to +70°C)
• Extended temperature (–40°C to +85°C)
Notes: 1. For part numbers and device markings, see
Figure 2 on page 2.
PDF: 09005aef81dc05df / Source: 09005aef821d5f08
1gb_nand_m48a__1.fm - Rev. 2.0 6/06 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
1 page  
www.DataSheet4U.com
Micron Confidential and Proprietary
Advance
1Gb: x8, x16 NAND Flash Memory
List of Figures
Figure 57:
Figure 58:
Figure 59:
Figure 60:
Figure 61:
Figure 62:
Figure 63:
Figure 64:
Figure 65:
Figure 66:
Figure 67:
Figure 68:
Figure 69:
Figure 70:
PAGE READ CACHE MODE Timing Diagram, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
PAGE READ CACHE MODE Timing Diagram, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
PAGE READ CACHE MODE Timing without R/B#, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
PAGE READ CACHE MODE Timing without R/B#, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
PROGRAM Operation with CE# “Don’t Care” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
PROGRAM PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
PROGRAM PAGE Operation with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
PROGRAM PAGE CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
PROGRAM PAGE CACHE MODE Ending on 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
63-Ball VFBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
PDF: 09005aef81dc05df / Source: 09005aef821d5f08
1gb_nand_m48aLOF.fm - Rev. 2.0 6/06 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
5 Page 
www.DataSheet4U.com
Architecture
Addressing
Micron Confidential and Proprietary
Advance
1Gb: x8, x16 NAND Flash Memory
Architecture
The MT29F1G08 and MT29F1G16 use NAND Flash electrical and command interfaces.
Data, commands, and addresses are multiplexed onto the same pins. This provides a
memory device with low pin count.
The internal memory array is accessed on a page basis. When performing reads, a page
of data is copied from the memory array into the data register. Once copied to the data
register, data is output sequentially, byte by byte on the x8 device, or word by word on
the x16 device.
The memory array is programmed on a page basis. After the starting address is loaded
into the internal address register, data is sequentially written to the internal data register
up to the end of a page. After all page data has been loaded into the data register, array
programming is started.
In order to increase programming bandwidth, this device incorporates a cache register.
In the cache programming mode, data is first copied into the cache register and then
into the data register. Once the data is copied into the data register, programming
begins. After the data register has been loaded and programming started, the cache reg-
ister becomes available for loading additional data. Loading the next page of data into
the cache register takes place while page programming is in process.
The INTERNAL DATA MOVE command also uses the internal cache register. Normally,
moving data from one area of external memory to another uses a large number of exter-
nal memory cycles. By using the internal cache register and data register, array data can
be copied from one page and then programmed into another without using external
memory cycles.
The MT29F1G08 and MT29F1G16 devices do not have dedicated address pins.
Addresses are loaded using a four-cycle sequence as shown in Tables 2 and 3. Table 2
presents address functions internal to the MT29F1G08 device; Table 3, the MT29F1G16.
See Figures 8 and 9 on pages 14 and 15 for additional memory mapping and addressing
details.
PDF: 09005aef81dc05df / Source: 09005aef821d5f08
1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
11 Page | ||
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