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PDF MAX9209 Data sheet ( Hoja de datos )
| Número de pieza | MAX9209 | |
| Descripción | (MAX9209 - MAX9215) Programmable DC-Balanced 21-Bit Serializers | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-2828; Rev 2; 2/04
Programmable DC-Balanced
21-Bit Serializers
General Description
The MAX9209/MAX9211/MAX9213/MAX9215 serialize
21 bits of LVTTL/LVCMOS parallel input data to three
LVDS outputs. A parallel rate clock on a fourth LVDS
output provides timing for deserialization.
The MAX9209/MAX9211/MAX9213/MAX9215 feature
programmable DC balance, which allows isolation
between the serializer and deserializer using AC-cou-
pling. The DC balance circuits on each channel code
the data, limiting the imbalance of transmitted ones and
zeros to a defined range. The companion MAX9210/
MAX9212/MAX9214/MAX9216 deserializers decode the
data. When DC balance is not programmed, the serial-
izers are compatible with non-DC-balanced, 21-bit seri-
alizers like the DS90CR215 and DS90CR217.
Two frequency ranges and two DC-balance default
conditions are available for maximum replacement flexi-
bility and compatibility with existing non-DC-balanced
serializers.
The MAX9209/MAX9211/MAX9213/MAX9215 are avail-
able in TSSOP and space-saving thin QFN packages,
and operate from a single +3.3V supply over the -40°C
to +85°C temperature range.
Applications
Automotive Navigation Systems
Automotive DVD Entertainment Systems
Digital Copiers
Laser Printers
Functional Diagram
MAX9209
MAX9211
MAX9213
MAX9215
LVDS DRIVER 0
TxOUT0+
TxIN 0 - 20
21
TIMING
CONTROL
PARALLEL-TO- LVDS DRIVER 1
SERIAL
TxOUT0-
TxOUT1+
CONVERTER
DCB/NC
AND
DC-BALANCE
TxOUT1-
LOGIC
LVDS DRIVER 2
TxOUT2+
TxCLK IN
PLL
7X OR 9X
CLOCK
GENERATOR
LVDS CLK
TxOUT2-
TxCLK OUT+
TxCLK OUT-
Features
♦ Programmable DC-Balanced or Non-DC-Balanced
Operation
♦ DC Balance Allows AC-Coupling for Ground-Shift
Tolerance
♦ As Low as 8MHz Operation
♦ Pin Compatible with DS90CR215 and DS90CR217
in Non-DC-Balanced Mode
♦ Integrated 110Ω (DC-Balanced) and 410Ω (Non-
DC-Balanced) Output Resistors
♦ 5V Tolerant LVTTL/LVCMOS Data Inputs
♦ PLL Requires No External Components
♦ Up to 1.785Gbps Throughput
♦ LVDS Outputs Meet IEC 61000-4-2 and ISO 10605
Requirements
♦ LVDS Outputs Conform to ANSI TIA/EIA-644
LVDS Standard
♦ Low-Profile 48-Lead TSSOP and Space-Saving
QFN Packages
♦ -40°C to +85°C Operating Temperature Range
♦ +3.3V Supply
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX9209ETM*
-40°C to +85°C 48 Thin QFN-EP**
MAX9209EUM
-40°C to +85°C 48 TSSOP
MAX9211ETM*
-40°C to +85°C 48 Thin QFN-EP**
MAX9211EUM*
-40°C to +85°C 48 TSSOP
MAX9213ETM*
-40°C to +85°C 48 Thin QFN-EP**
MAX9213EUM
-40°C to +85°C 48 TSSOP
MAX9215ETM*
-40°C to +85°C 48 Thin QFN-EP**
MAX9215EUM*
-40°C to +85°C 48 TSSOP
*Future product—contact factory for availability.
**EP = Exposed pad.
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Programmable DC-Balanced
21-Bit Serializers
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 5pF, PWRDWN = high, DCB/NC = high or low, TA = -40°C to +85°C, unless otherwise
noted. Typical values are at VCC = +3.3V, TA = +25°C.) (Notes 4, 5)
PARAMETER
TxCLK IN High Time
TxCLK IN Low Time
TxIN to TxCLK IN Setup
TxIN to TxCLK IN Hold
TxCLK IN to TxCLK OUT Delay
SYMBOL
TCIH
TCIL
TSTC
THTC
TCCD
CONDITIONS
Figure 7
Figure 7
Figure 7
Figure 7
Non-DC-balanced mode, Figure 8
DC-balanced mode, Figure 8
MIN
TYP
MAX UNITS
0.3 x TCIP
0.7 x TCIP ns
0.3 x TCIP
0.7 x TCIP ns
2.2 ns
0 ns
3.5 4.5 6.0
ns
4.7 5.9 7.2
Serializer Phase-Locked Loop Set TPLLS Figure 9
32800 x
TCIP
ns
Serializer Power-Down Delay
TPDD Figure 10
14 50 ns
TxCLK IN Cycle-to-Cycle Jitter
(Input Clock Requirement)
TJIT
2 ns
Magnitude of Differential Output
Voltage
VOD 595Mbps data rate, worst-case pattern
250
mV
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VOD , ∆VOD, and ∆VOS.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA = +25°C.
Note 3: Guaranteed by design.
Note 4: TCIP is the period of TxCLK IN.
Note 5: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 6: Pulse position TPPosN is characterized using 27 - 1 PRBS data.
Typical Operating Characteristics
(VCC = +3.3V, RL = 100Ω ±1%, CL = 5pF, PWRDWN = high, TA = +25°C, unless otherwise noted.)
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
100
MAX9209
DC-BALANCED MODE
80
WORST-CASE
PATTERN
60
27 - 1 PRBS
40
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
100
MAX9209
NON-DC-BALANCED MODE
80
WORST-CASE
60 PATTERN
40
27 - 1 PRBS
WORST-CASE AND PRBS SUPPLY CURRENT
vs. FREQUENCY
120
MAX9213
NON-DC-BALANCED MODE
100
80 WORST-CASE
PATTERN
60
40 27 - 1 PRBS
20
0
10 20 30 40
FREQUENCY (MHz)
50
20
0
10 20 30 40 50 60
FREQUENCY (MHz)
20
15
30 45 60 75
FREQUENCY (MHz)
90
_______________________________________________________________________________________ 5
5 Page 
Programmable DC-Balanced
21-Bit Serializers
PWRDWN
VCC
TxCLK IN
TxOUT_, TxCLK OUT HIGH-Z
Figure 9. PLL Set Time
2.0V
3.0V
TPPLS
VOD = 0
PWRDWN
3.6V
0.8V
DIFFERENTIAL 0
TxCLK IN
TxOUT_, TxCLK OUT
Figure 10. Power-Down Delay
TPDD
HIGH-Z
TxCLK OUT+
TxCLK OUT-
CYCLE N - 1
CYCLE N
DCA2 DCB2 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 DCA2
TxOUT2
CYCLE N + 1
DCB2 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14
DCA1 DCB1
TxOUT1
TxIN13 TxIN12 TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
DCA1
DCB1 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9
TxIN8
TxIN7
DCA0 DCB0
TxOUT0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
DCA0
DCB0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
Figure 11. DC-Balanced Mode Inputs Mapped to LVDS Outputs
data channels is 10. At most, 10 more zeros than ones,
or 10 more ones than zeros, are transmitted. The maxi-
mum DSV for the clock channel is 5. Limiting the DSV
and choosing the correct coupling capacitors maintain
differential signal amplitude and reduce jitter due to
droop on AC-coupled links.
MAX9214/MAX9216 deserializers whether the data bits
are inverted (Figure 11). The deserializer restores the
original state of the parallel data. The LVDS clock signal
alternates duty cycles of 4/9 and 5/9, which maintains
DC balance. Figure 12 shows the non-DC-balanced
mode inputs mapped to LVDS outputs.
To obtain DC balance on the data channels, the parallel
input data is inverted or not inverted, depending on the
sign of the digital sum at the word boundary. Two com-
plementary bits are appended to each group of 7 paral-
lel input data bits to indicate to the MAX9210/MAX9212/
AC-Coupling Benefits
Bit errors experienced with DC-coupling can be elimi-
nated by increasing the receiver common-mode volt-
age range by AC-coupling. AC-coupling increases the
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MAX9209.PDF ] | |
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