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PDF MAX9207 Data sheet ( Hoja de datos )
| Número de pieza | MAX9207 | |
| Descripción | (MAX9205 / MAX9207) 10-Bit Bus LVDS Serializers | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX9207 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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EVALUATION KIT AVAILABLE
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
General Description
The MAX9205/MAX9207 serializers transform 10-bit-
wide parallel LVCMOS/LVTTL data into a serial high-
speed bus low-voltage differential signaling (LVDS)
data stream. The serializers typically pair with deserial-
izers like the MAX9206/MAX9208, which receive the
serial output and transform it back to 10-bit-wide paral-
lel data.
The MAX9205/MAX9207 transmit serial data at speeds
up to 400Mbps and 660Mbps, respectively, over PCB
traces or twisted-pair cables. Since the clock is recov-
ered from the serial data stream, clock-to-data and
data-to-data skew that would be present with a parallel
bus are eliminated.
The serializers require no external components and few
control signals. The input data strobe edge is selected
by TCLK_R/F. PWRDN is used to save power when the
devices are not in use. Upon power-up, a synchroniza-
tion mode is activated, which is controlled by two SYNC
inputs, SYNC1 and SYNC2.
The MAX9205 can lock to a 16MHz to 40MHz system
clock, while the MAX9207 can lock to a 40MHz to
66MHz system clock. The serializer output is held in
high impedance until the device is fully locked to the
local system clock, or when the device is in power-
down mode.
Both the devices operate from a single +3.3V supply,
are specified for operation from -40°C to +85°C, and
are available in 28-pin SSOP packages.
Applications
Cellular Phone Base
Stations
Add Drop Muxes
Digital Cross-Connects
DSLAMs
Network Switches and
Routers
Backplane Interconnect
Features
o Standalone Serializer (vs. SERDES) Ideal for
Unidirectional Links
o Framing Bits for Deserializer Resync Allow Hot
Insertion Without System Interruption
o LVDS Serial Output Rated for Point-to-Point and
Bus Applications
o Wide Reference Clock Input Range
16MHz to 40MHz (MAX9205)
40MHz to 66MHz (MAX9207)
o Low 140ps (pk-pk) Deterministic Jitter (MAX9207)
o Low 34mA Supply Current (MAX9205)
o 10-Bit Parallel LVCMOS/LVTTL Interface
o Up to 660Mbps Payload Data Rate (MAX9207)
o Programmable Active Edge on Input Latch
o Pin-Compatible Upgrades to DS92LV1021 and
DS92LV1023
Ordering Information
PART
TEMP
RANGE
PIN-
PACKAGE
REF CLOCK
RANGE
(MHz)
MAX9205EAI+ -40°C to +85°C 28 SSOP
16 to 40
MAX9205EAI/V+ -40°C to +85°C 28 SSOP
16 to 40
MAX9207EAI+ -40°C to +85°C 28 SSOP
40 to 66
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Pin Configuration and Functional Diagram appear at end of
data sheet.
Typical Application Circuit
10
IN_
TCLK_R/F
TCLK
SYNC 1
SYNC 2
OUT+
BUS
LVDS
IN+
100Ω
100Ω
10
OUT_
OUT- IN-
PLL
TIMING AND
CONTROL
PCB OR
TWISTED PAIR
EN
PWRDN
PLL
TIMING AND
CONTROL
REFCLK
EN
LOCK
MAX9205
MAX9207
MAX9206
MAX9208
CLOCK
RECOVERY
RCLK
RCLK_R/F
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-2029; Rev 2; 10/12
1 page  
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
PIN
1, 2
3–12
13
14
15, 16
17, 26
18, 20,
23, 25
19
21
22
24
27, 28
NAME
SYNC 1,
SYNC 2
IN0–IN9
TCLK_R/F
TCLK
DGND
AVCC
AGND
EN
OUT-
OUT+
PWRDN
DVCC
Pin Description
FUNCTION
LVCMOS/LVTTL Logic Inputs. The two SYNC pins are ORed. When at least one of the two pins
are asserted high for at least six cycles of TCLK, the serializer initiates a transmission of 1024
SYNC patterns. If held high after 1024 SYNC patterns have been transmitted, SYNC patterns
continue to be sent until the SYNC pin is asserted low. Toggling a SYNC pin after six TCLK cycles
high and before 1024 SYNC patterns have been transmitted does not affect the output of the 1024
SYNC patterns.
LVCMOS/LVTTL Data Inputs. Data is loaded into a 10-bit latch by the selected TCLK edge.
LVCMOS/LVTTL Logic Input. High selects a TCLK rising-edge data strobe. Low selects a TCLK
falling-edge data strobe.
LVCMOS/LVTTL Reference Clock Input. The MAX9205 accepts a 16MHz to 40MHz clock. The
MAX9207 accepts a 40MHz to 66MHz clock. TCLK provides a frequency reference to the PLL and
strobes parallel data into the input latch.
Digital Circuit Ground. Connect to ground plane.
Analog Circuit Power Supply (Includes PLL). Bypass AVCC to ground with a 0.1µF capacitor and a
0.001µF capacitor. Place the 0.001µF capacitor closest to AVCC.
Analog Circuit Ground. Connect to ground plane.
LVCMOS/LVTTL Logic Input. High enables serial data output. Low puts the bus LVDS output into
high impedance.
Inverting Bus LVDS Differential Output
Noninverting Bus LVDS Differential Output
LVCMOS/LVTTL Logic Input. Low puts the device into power-down mode and the output into high
impedance.
Digital Circuit Power Supply. Bypass DVCC to ground with a 0.1µF capacitor and a 0.001µF
capacitor. Place the 0.001µF capacitor closest to DVCC.
Detailed Description
The MAX9205/MAX9207 are 10-bit serializers designed
to transmit data over balanced media that may be a
standard twisted-pair cable or PCB traces at 160Mbps
to 660Mbps. The interface may be double-terminated
point-to-point or a heavily loaded multipoint bus. The
characteristic impedance of the media and connected
devices can range from 100Ω for a point-to-point inter-
face to 54Ω for a heavily loaded multipoint bus. A dou-
ble-terminated point-to-point interface uses a
100Ω-termination resistor at each end of the interface,
resulting in a load of 50Ω. A heavily loaded multipoint
bus requires a termination as low as 54Ω at each end
of the bus, resulting in a termination load of 27Ω. The
serializer requires a deserializer such as the
MAX9206/MAX9208 for a complete data transmission
application.
A high-state start bit and a low-state stop bit, added
internally, frame the 10-bit parallel input data and
ensure a transition in the serial data stream. Therefore,
12 serial bits are transmitted for each 10-bit parallel
input. The MAX9205 accepts a 16MHz to 40MHz refer-
ence clock, producing a serial data rate of 192Mbps
(12 bits x 16MHz) to 480Mbps (12 bits x 40MHz). The
MAX9207 accepts a 40MHz to 66MHz reference clock,
producing 480Mbps to 792Mbps. However, since only
10 bits are from input data, the actual throughput is 10
times the TCLK frequency.
To transmit data, the serializers sequence through
three modes: initialization mode, synchronization mode,
and data transmission mode.
Maxim Integrated
5
5 Page 
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
A point-to-point version of the multidrop bus is shown in
Figure 13. The low-jitter MAX9150 10-port repeater is
used to reproduce and transmit the serializer output
over 10 double-terminated point-to-point links.
Compared to the multidrop bus, more interconnect is
traded for more robust hot-plug capability.
The repeater eliminates nine serializers compared to 10
individual point-to-point serializer-to-deserializer con-
nections. Since repeater jitter subtracts from the serial-
izer-deserializer timing margin, a low-jitter repeater is
essential in most high data rate applications.
Multiple serializers and deserializers bused over a dif-
ferential serial connection on a backplane are shown in
Figure 14. The second serializer can be a backup to
the primary serializer. The typical close spacing (1in or
less) of cards on a backplane reduces the characteris-
tic impedance by as much as half the initial, unloaded
value. Termination resistors that match the loaded char-
acteristic impedance are required at each end of the
bus. The total loaded seen by the serializer is 27Ω in
this case.
Board Layout
For bus LVDS applications, a four-layer PCB that pro-
vides separate power, ground, and input/output signals
is recommended. Separate LVTTL/LVCMOS and bus
LVDS signals from each other to prevent coupling into
the bus LVDS lines.
ASIC ASIC
ASIC
MAX9205
MAX9207
MAX9150
REPEATER
MAX9206
MAX9208
100Ω
100Ω
100Ω
Figure 13. Point-to-Point Broadcast Using MAX9150 Repeater
MAX9206
MAX9208
100Ω
Maxim Integrated
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet MAX9207.PDF ] | |
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