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PDF MAX4926 Data sheet ( Hoja de datos )
| Número de pieza | MAX4926 | |
| Descripción | (MAX4923 - MAX4926) Overvoltage Protectors | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-0810; Rev 0; 4/07
Overvoltage Protectors with
External pFET
General Description
The MAX4923–MAX4926 overvoltage protection
(OVP) controllers protect low-voltage systems against
high-voltage faults of up to +28V with an appropriate
external pFET. When the input voltage exceeds the over-
voltage lockout (OVLO) threshold, or falls below the
undervoltage lockout (UVLO) threshold, these devices
turn off the pFET to prevent damage to protected compo-
nents and issue a flag to notify the processor of a fault
condition.
The typical overvoltage trip level is set to 7.18V
(MAX4923), 6.16V (MAX4924), 5.65V (MAX4925), and
4.46V (MAX4926). The undervoltage trip level is set to
2.44V (typ) for all devices.
The input (IN) is ESD protected to ±15kV HBM when
bypassed to ground with a 1µF ceramic capacitor. All
devices are offered in a small, 6-pin (1.5mm x 1.0mm)
µDFN package and are specified over the extended
-40°C to +85°C temperature range.
Applications
Cell Phones
Digital Still Cameras
PDAs and Palmtop Devices
MP3 Players
Pin Configuration
TOP VIEW
N.C N.C GATE
6 54
Features
o Overvoltage Protection Up to +28V
o Preset 7.18V, 6.16V, 5.65V, and 4.46V Typical
Overvoltage Trip Levels
o Preset 2.44V Typical Undervoltage Trip Level
o ±2.5% Accurate Overvoltage/Undervoltage
Trip Levels
o Low 13µA (typ) Supply Current
o Drives External pFET
o 20ms Adapter Debounce Time
o Fault Flag Indicator
o 6-Pin (1.5mm x 1.0mm) µDFN Package
Typical Operating Circuit
INPUT
+1.8V TO 28V
1μF
P OUTPUT
1
IN
4
GATE
MAX4923–MAX4926
VIO
MA4923–MAX4926
2
GND
3
FLAG
123
IN GND FLAG
μDFN
Ordering Information/Selector Guide
PART
PIN-PACKAGE
OVLO (V)
UVLO (V)
TOP MARK
PKG CODE
MAX4923ELT+*
6 μDFN
7.18
2.44
LB
L611-1
MAX4924ELT+
6 μDFN
6.16
2.44
LC
L611-1
MAX4925ELT+
6 μDFN
5.65
2.44
LD
L611-1
MAX4926ELT+
6 μDFN
4.46
2.44
LE
L611-1
Note: All devices are specified over the -40°C to +85°C operating temperature range.
+Denotes lead-free package.
*Future Product—contact factory for availability.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Overvoltage Protectors with
External pFET
STANDBY
GATE = HIGH
FLAG = HIGH
VUVLO < VIN < VOVLO
VIN < VUVLO
TIME STARTS
COUNTING
t = 20ms
VIN > VOVLO
ON
GATE = LOW
FLAG = LOW
Figure 2. State Machine
Detailed Description
The MAX4923–MAX4926 overvoltage protection
controllers protect low-voltage systems against high-
voltage faults of up to +28V when used with a -30V
pFET. When the input voltage exceeds the OVLO
threshold, these devices turn off the external pFET to
prevent damage to protected components.
The typical overvoltage trip level is set to 7.18V
(MAX4923), 6.16V (MAX4924), 5.65V (MAX4925), and
4.46V (MAX4926). When the supply drops below the
UVLO threshold, the devices turn off the external pFET.
IN is ESD protected to +15kV (Human Body Model) when
bypassed with a 1µF ceramic capacitor to ground.
Undervoltage Lockout (UVLO)
The MAX4923–MAX4926 have a fixed 2.44V (typ)
UVLO level. When VIN is less than VUVLO, GATE is high
and FLAG is high.
Overvoltage Lockout (OVLO)
The MAX4923 has a 7.18V (typ) OVLO; the MAX4924
has a 6.16V (typ) OVLO; the MAX4925 has a 5.65V
(typ) OVLO; and the MAX4926 has a 4.46V (typ) OVLO.
When VIN is greater than VOVLO, GATE is high and
FLAG is high.
FLAG Output
The open-drain FLAG output is used to signal to the
host system that there is a fault with the input voltage.
FLAG goes high during an overvoltage or undervoltage
fault. Connect a pullup resistor from FLAG to the logic
I/O voltage of the host system.
ADAPTER WITH
BUILT-IN
BATTERY
CHARGER
INPUT
1
IN
P OUTPUT
4
GATE
LITHIUM ION
BATTERY
SYSTEM
+ LOADS
-
MAX4926
VI0
2
GND
3
FLAG
Figure 3. MAX4926 Typical Operating Circuit
Device Operation
The MAX4923–MAX4926 have an on-board state
machine to control device operation. A flowchart is
shown in Figure 2. At initial power up, if VIN < VUVLO or
if VIN > VOVLO, both GATE and FLAG are high. When
VUVLO < VIN < VOVLO, an internal timer starts counting
and the device enters its on state after a 20ms delay. At
any time if VIN drops below VUVLO or above VOVLO,
both GATE and FLAG transition high.
Application Information
MAX4926 Application
In a typical application for the MAX4926, an external
adapter with built-in battery charger is connected to IN
and a battery is connected to the drain of the external
FET. When the adapter is unplugged, IN is directly con-
nected to the battery through the external FET. Since
the battery voltage is typically greater than VUVLO, the
GATE voltage stays low and the device remains pow-
ered by the battery.
MOSFET Selection
The MAX4923–MAX4926 are designed for use with
either a single pFET or dual pFETs in parallel.
MOSFETs with RDS(ON) specified for a VGS of -4.5V are
recommended. For input supplies near the UVLO maxi-
mum of 2.5V, use a MOSFET specified for a lower VGS
voltage. Also, the VDS must be -30V and the VGS (max)
must be higher than the VOVLO (max) for the MOSFET
to withstand the full +28V input range of the
MAX4923–MAX4926.
_______________________________________________________________________________________ 5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MAX4926.PDF ] | |
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