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PDF MC14510B Data sheet ( Hoja de datos )
| Número de pieza | MC14510B | |
| Descripción | BCD Up/Down Counter | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
www.DSatEaSMhIeCetO4UN.cDoUmCTOR TECHNICAL DATA
MC14510B
BCD Up/Down Counter
The MC14510B synchronous up/down BCD counter is constructed with
MOS P–channel and N–channel enhancement mode devices in a monolithic
structure. The counter consists of type D flip–flop stages with a gating
structure to provide type T flip–flop capability.
This counter can be preset by applying the desired value in BCD to the
Preset inputs (P1, P2, P3, P4) and then bringing the Preset Enable (PE)
high. The direction of counting is controlled by applying a high (for up
counting) or a low (for down counting) to the UP/DOWN input. The state of
the counter changes on the positive transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q1, Q2, Q3, Q4) can be reset to a low state by applying a high to the
Reset (R) pin.
This CMOS counter finds primary use in up/down and difference counting.
Other applications include: (1) Frequency synthesizer applications where
low power dissipation and/or high noise immunity is desired, (2) Analog–to–
digital and digital–to–analog conversions, and (3) Magnitude and sign
generation.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Internally Synchronous for High Speed
• Logic Edge–Clocked Design — Count Occurs on Positive Going Edge
of Clock
• Asynchronous Preset Enable Operation
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΕ Capable of Driving Two Low–power TTL Loads or One Low–power
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSchottky TTL Load Over the Rated Temperature Range.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS* (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
VDD DC Supply Voltage
– 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin
PD Power Dissipation, per Package†
500 mW
Tstg Storage Temperature
– 65 to + 150
_C
TL Lead Temperature (8–Second Soldering)
260 _ C
* Maximum Ratings are those values beyond which damage to the may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_ C From 65_ C To 125_ C
Ceramic “L” Packages: – 12 mW/_ C From 100_ C To 125_ C
TRUTH TABLE
Preset
Carry In Up/Down Enable
Reset
Clock
Action
1 X 0 0 X No Count
0 1 00
Count Up
0 0 00
Count Down
X X 10X
Preset
X X X1X
Reset
X = Don’t Care
NOTE: When counting up, the Carry Out signal is normally high, and is low only
when Q1 and Q4 are high and Carry In is low. When counting down, Carry
Out is low only when Q1 through Q4 and Carry In are low.
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
BLOCK DIAGRAM
1 PE
Q1 6
5 CARRY IN
9R
Q2 11
10 UP/DOWN
15 CLOCK Q3 14
4 P1
12 P2
Q4 2
13 P3
3
P4
CARRY
OUT
7
VDD = PIN 16
VSS = PIN 8
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
v voperation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
MC14510B
351
1 page  
www.DataSheet4U.com
RESET
PRESET ENABLE
CLOCK
CARRY OUT
LOGIC DIAGRAM
P1 Q1
46
P2 Q2
12 11
P3 Q3
13 14
P4 Q4
32
PEP Q
C
DQ
PEP Q
C
DQ
PEP Q
C
DQ
PEP Q
C
DQ
CARRY IN
UP/DOWN
STATE DIAGRAM FOR UP COUNTING
0 1 23 4
15 5
14 6
13 7
12 11 10 9
8
STATE DIAGRAM FOR DOWN COUNTING
0 1 23 4
15 5
14 6
13 7
12 11 10 9
8
MOTOROLA CMOS LOGIC DATA
MC14510B
355
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