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PDF MCF5475 Data sheet ( Hoja de datos )
| Número de pieza | MCF5475 | |
| Descripción | Integrated Microprocessor Electrical Characteristics | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF5475EC
Rev. 3, 03/2007
MCF5475
TEPBGA–388
MCF5475 Integrated
Microprocessor Electrical
Characteristics
This chapter contains electrical specification tables and
reference timing diagrams for the MCF5475 microprocessor.
This section contains detailed information on power
considerations, DC/AC electrical characteristics, and AC
timing specifications of the MCF5475.
MCF547X Family Features:
• ColdFire V4e Core
– Limited superscalar V4 ColdFire processor core
– Up to 266 MHz peak internal core frequency (410 MIPS
(Dhrystone 2.1) @ 266 MHz)
– Harvard architecture
– 32-Kbyte instruction cache
– 32-Kbyte data cache
– Memory Management Unit (MMU)
– Floating point unit (FPU)
• Internal master bus (XLB) arbiter
• 32-bit double data rate (DDR) synchronous DRAM
(SDRAM) controller
– 66–133 MHz operation
• Version 2.2 peripheral component interconnect (PCI) bus
• Flexible multi-function external bus (FlexBus)
• Communications I/O subsystem
– Intelligent 16 channel DMA controller, with support for
– Dedicated DMA channels for receive and transmit on
all subsystem peripheral interfaces
– Up to two (2) 10/100 Mbps fast Ethernet controllers
(FECs)
– Universal serial bus (USB) version 2.0 device controller
– Up to four (4) programmable serial controllers (PSCs)
for UART, USART, modem, codec, and IrDA 1.1
interfaces
– I2C peripheral interface
– DMA Serial Peripheral Interface (DSPI)
• Optional Cryptography accelerator module
– DES/3DES block cipher
– AES block cipher
– RC4 stream cipher
– MD5/SHA-1/SHA-256/HMAC hashing
– Random Number Generator
• 32-Kbyte system SRAM
• System integration unit (SIU)
– Interrupt controller
– Watchdog timer
– Two (2) 32-bit slice timers
– Up to four (4) 32-bit general-purpose timers
– General-purpose I/O ports multiplexed with peripheral
pins
• Debug and test features
– ColdFire background debug mode (BDM) port
– JTAG/ IEEE 1149.1 test access port
• PLL and clock generator
– 30 to 66.67 MHz input frequency range
© Freescale Semiconductor, Inc., 2007. All rights reserved.
1 page  
DC Electrical Specifications
2.2 Thermal Resistance
Table 3 lists thermal resistance values.
Table 3. Thermal Resistance
Characteristic
Symbol
Value
Unit
388 pin TEPBGA — Junction to ambient, natural Four layer board (2s2p)
convection
θJMA
20–221,2
°C/W
Junction to ambient (@200 ft/min)
Four layer board (2s2p)
θJMA
231,2
°C/W
Junction to board
— θJB 153 °C/W
Junction to case
— θJC 104 °C/W
Junction to top of package
Natural convection
Ψjt 21,5 °C/W
1 Τhe θJA and Ψjt parameters are simulated in accordance with EIA/JESD Standard 51-2 for natural convection.
Freescale recommends the use of θJA and power dissipation specifications in the system design to prevent device
junction temperatures from exceeding the rated specification. System designers should be aware that device
junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the
device junction temperature specification can be verified by physical measurement in the customer’s system using
the Ψjt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.
2 Per JEDEC JESD51-6 with the board horizontal.
3 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
4 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5 Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written as Psi-JT.
3 DC Electrical Specifications
Table 4 lists DC electrical operating temperatures. This table is based on an operating voltage of EVDD = 3.3 VDC ± 0.3 VDC
and IVDD of 1.5 ± 0.07 VDC.
Table 4. DC Electrical Specifications
Characteristic
Symbol
External (I/O pads) operation voltage range
EVDD
Memory (I/O pads) operation voltage range (DDR Memory)
Internal logic operation voltage range1
PLL Analog operation voltage range1
SD VDD
IVDD
PLL VDD
USB oscillator operation voltage range
USB_OSVDD
USB digital logic operation voltage range
USBVDD
USB PHY operation voltage range
USB_PHYVDD
USB oscillator analog operation voltage range
USB_OSCAVDD
USB PLL operation voltage range
Input high voltage SSTL 3.3V/2.5V2
USB_PLLVDD
VIH
Min
3.0
2.30
1.43
1.43
3.0
3.0
3.0
1.43
1.43
VREF + 0.3
Max
3.6
2.70
1.58
1.58
3.6
3.6
3.6
1.58
1.58
SD VDD + 0.3
Units
V
V
V
V
V
V
V
V
V
V
MCF5475 Integrated Microprocessor Electrical Characteristics, Rev. 3
Freescale Semiconductor
5
5 Page 
6 PLL Timing Specifications
The specifications in Table 7 are for the CLKIN pin.
Table 7. Clock Timing Specification
Num
Characteristic
Min Max
C1 Cycle time
C2 Rise time (20% of VDD to 80% of VDD)
C3 Fall time (80% of VDD to 20% of VDD)
C4 Duty cycle (at 50% of VDD)
15.0
—
—
40
40
2
2
60
PLL Timing Specifications
Units
ns
ns
ns
%
C1
CLKIN
C4 C4
C2
C3
Figure 8. Input Clock Timing Diagram
Table 8 shows the supported PLL encodings.
Table 8. MCF547X Divide Ratio Encodings
AD[12:8]1
CLKIN—PCI and FlexBus
Clock Ratio
Frequency Range
(MHz)
Internal XLB, SDRAM
Bus, and PSTCLK
Frequency Range
(MHz)
Core Frequency Range
(MHz)
00011
00101
1:2
1:2
41.6–66.66
25.0–44.4
83.33–133.33
50.0–88.82
166.66–266.66
100.0–177.66
01111
1:4
25.0–33.3
100–133.33
200–266.66
1 All other values of AD[12:8] are reserved.
2 DDR memories typically have a minimum speed of 83 MHz. Some vendors specify down to 75 MHz. Check with
memory component specifications to verify.
Figure 9 correlates CLKIN, internal bus, and core clock frequencies for the 1x–4x multipliers.
CLKIN
Internal Clock
Core Clock
2x
25.0 66.66
50.0
2x
133.33
100.0
266.66
25.0 33.33
4x
25 50 70
CLKIN (MHz)
30
100.0
2x
133.33
200.0
266.66
50 70 90 110 130
60 80 100 120 140 160 180 200 220 240 260
Internal Clock (MHz)
Core Clock (MHz)
Figure 9. CLKIN, Internal Bus, and Core Clock Ratios
MCF5475 Integrated Microprocessor Electrical Characteristics, Rev. 3
Freescale Semiconductor
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MCF5475.PDF ] | |
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