PDF CY28416 Data sheet ( Hoja de datos )

Número de pieza	CY28416
Descripción	Next Generation FTG
Fabricantes	Cypress Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de CY28416 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas
No Preview Available ! www.DataSheet4U.com PRELIMINARY CY28416 Next Generation FTG for Intel® Architecture Features • Supports Intel Pentium®4-Type CPUs • Selectable CPU Frequencies • Two Differential CPU Clock Pairs • Four 100-MHz Differential SRC Clock Pairs • One CPU/SRC Selectable Differential Clock Pair • One 96-MHz Differential Dot Clock Support • Two 48-MHz Clocks • Four 33-MHz PCI Clocks • Two 33-MHz PCI Free Running Clocks • Low Voltage Frequency Select Input • I2C Support Byte/Word/Block Read/Write Capabilities • Ideal Lexmark Spread Spectrum Profile for Maximum EMI Reduction • 3.3V Power Supply • 48-pin SSOP Package CPU SRC x2 / x3 x4 / x5 PCI x6 DOT x1 USB x2 REF x2 Block Diagram XIN XOUT FS_[C:A] VTT_PWRGD# IREF XTAL OSC PLL Ref Freq PLL1 Divider Network PD PLL2 SDATA SCLK I2C Logic Pin Configuration VDD_REF REF VDD_CPU CPUT[0:1], CPUC[0:1], CPU2/SRC4 VDD_SRC SRCT[0:3], SRCC[0:3] VDD_PCI PCI[0:3] VDD_PCIF PCIF[0:1] VDD_48MHz DOT96T DOT96C 48MHz0 48MHz1 SCLK SDATA XOUT XIN VSS_REF REF1/FS_A REF0/FS_C VDD_REF PCI0 PCI1 VDD_PCI VSS_PCI PCI2 PCI3 VSS_PCI VDD_PCI PCIF0/TESTSEL PCIF1/ITPEN VDD_48 48MHz0/FS_B 48MHz1 VSS_48 DOT96T DOT96C 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 48-PIN SSOP VSS_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 IREF VSSA VDDA CPUT2_ITP/SRCT4 CPUC2_ITP/SRCC4 VDD_SRC VSS_SRC SRCT3 SRCC3 VDD_SRC SRCC2_SATA SRCT2_SATA SRCC1 SRCT1 VSS_SRC SRCC0 SRCT0 VTT_PWRGD#/PD Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-07657 Rev. A Revised February 2, 2005 1 page PRELIMINARY CY28416 Byte 1: Control Register 1 Bit @Pup 71 61 Name RESERVED DOT_96T/C 5 1 48 MHz0, 48 MHz1 41 REF0 31 REF1 21 CPU[T/C]1 11 CPU[T/C]0 00 Byte 2: Control Register 2 Bit @Pup 71 CPUT/C SRCT/C PCIF PCI Name PCI3 61 PCI2 51 41 31 RESERVED RESERVED PCI1 21 PCI0 11 PCIF1 01 PCIF0 Byte 3: Control Register 3 Bit @Pup 70 60 50 40 30 20 10 00 Name SRC[T/C]4 RESERVED RESERVED SRC[T/C]3 SRC2_SATA SRC[T/C]1 SRC[T/C]0 RESERVED Description RESERVED, Set = 1 DOT_96 MHz Output Enable 0 = Disable (Hi-Z), 1 = Enabled 48 MHz Output Enable 0 = Disabled, 1 = Enabled REF Output Enable 0 = Disabled, 1 = Enabled REF Output Enable 0 = Disabled, 1 = Enabled CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enabled CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enabled Spread Spectrum Enable 0 = Spread off, 1 = Spread on PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled RESERVED, Set = 1 RESERVED, Set = 1 PCI1 Output Enable 0 = Disabled, 1 = Enabled PCI0 Output Enable 0 = Disabled, 1 = Enabled PCIF2 Output Enable 0 = Disabled, 1 = Enabled PCIF1 Output Enable 0 = Disabled, 1 = Enabled Description Description Allow control of SRC[T/C]4 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# RESERVED, Set = 0 RESERVED, Set = 0 Allow control of SRC[T/C]3 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC2_SATA with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]1 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]1 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# RESERVED, Set = 0 Document #: 38-07657 Rev. A Page 5 of 15 5 Page PRELIMINARY CY28416 AC Electrical Specifications Parameter Description Condition Crystal TDC XIN Duty Cycle The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification TPERIOD XIN Period When XIN is driven from an external clock source TR / TF XIN Rise and Fall Times Measured between 0.3VDD and 0.7VDD TCCJ XIN Cycle to Cycle Jitter As an average over 1-µs duration LACC Long-term Accuracy Over 150 ms CPU at 0.7V TDC CPUT and CPUC Duty Cycle Measured at crossing point VOX TPERIOD 100-MHz CPUT and CPUC Period Measured at crossing point VOX TPERIOD 133-MHz CPUT and CPUC Period Measured at crossing point VOX TPERIOD 166-MHz CPUT and CPUC Period Measured at crossing point VOX TPERIOD 200-MHz CPUT and CPUC Period Measured at crossing point VOX TPERIOD 266-MHz CPUT and CPUC Period Measured at crossing point VOX TPERIOD 333-MHz CPUT and CPUC Period Measured at crossing point VOX TPERIOD 400-MHz CPUT and CPUC Period Measured at crossing point VOX TPERIODSS 100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TPERIODSS 133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TPERIODSS 166-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TPERIODSS 200-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TPERIODSS 266-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TPERIODSS 333-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TPERIODSS 400-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TSKEW Any CPUT/C to CPUT/C Clock Skew, Measured at crossing point VOX SSC TCCJ TCCJ TR / TF TRFM ∆TR ∆TF VHIGH VLOW VOX VOVS CPUT/C Cycle to Cycle Jitter CPU2/SRC4 Cycle to Cycle Jitter CPUT and CPUC Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2(TR – TF)/(TR + TF) Math averages Figure 7 Math averages Figure 7 Min. 47.5 69.841 – – – 45 9.9970 7.4978 5.9982 4.9985 3.7489 2.9991 2.4993 9.9970 7.4978 5.9982 4.9985 3.7489 2.9991 2.4993 – – – 175 – – – 660 –150 250 – VUDS Minimum Undershoot Voltage VRB Ring Back Voltage See Figure 7. Measure SE SRC TDC SRCT and SRCC Duty Cycle Measured at crossing point VOX TPERIOD 100-MHz SRCT and SRCC Period Measured at crossing point VOX TPERIODSS 100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX TSKEW Any SRCT/C to SRCT/C Clock Skew Measured at crossing point VOX TCCJ SRCT/C Cycle to Cycle Jitter Measured at crossing point VOX –0.3 – 45 9.9970 9.9970 – – Max. Unit 52.5 % 71.0 ns 10.0 ns 500 ps 300 ppm 55 10.003 7.5023 6.0018 5.0015 3.7511 3.0009 2.5008 10.0533 7.5400 6.0320 5.0266 3.7700 3.0160 2.5133 100 % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps 85 125 700 20 125 125 850 – 550 VHIGH + 0.3 – 0.2 ps ps ps % ps ps mv mv mv V V V 55 10.003 10.0533 100 125 % ns ns ps ps Document #: 38-07657 Rev. A Page 11 of 15 11 Page

Páginas	Total 15 Páginas
PDF Descargar	[ Datasheet CY28416.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
CY28410	Clock Generator for Intel Grantsdale Chipset	Cypress Semiconductor
CY28410-2	Clock Generator	Cypress Semiconductor
CY28410-2	Clock Generator	SpectraLinear
CY28411	Clock Generator for Intel Alviso Chipset	Cypress Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar