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PDF LTC2615 Data sheet ( Hoja de datos )
| Número de pieza | LTC2615 | |
| Descripción | (LTC2605 - LTC2625) Octal 16-Bit Rail-to-Rail DACs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2615 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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LTC2605/LTC2615/LTC2625
Octal 16-/14-/12-Bit
Rail-to-Rail DACs in 16-Lead SSOP
FEATURES
DESCRIPTIO
■ Smallest Pin-Compatible Octal DACs:
LTC2605: 16 Bits
LTC2615: 14 Bits
LTC2625: 12 Bits
■ Guaranteed Monotonic Over Temperature
■ 400kHz I2C Interface
■ Wide 2.7V to 5.5V Supply Range
■ Low Power Operation: 250µA per DAC at 3V
■ Individual Channel Power-Down to 1µA, Max
■ Ultralow Crosstalk Between DACs (<10µV)
■ High Rail-to-Rail Output Drive (±15mA, Min)
■ Double-Buffered Digital Inputs
■ 27 Selectable Addresses
■ LTC2605/LTC2615/LTC2625: Power-On Reset to
Zero Scale
■ LTC2605-1/LTC2615-1/LTC2625-1: Power-On Reset
to Midscale
■ Tiny 16-Lead Narrow SSOP Package
www.DataSheet4U.com
U
APPLICATIO S
■ Mobile Communications
■ Process Control and Industrial Automation
■ Instrumentation
■ Automatic Test Equipment
The LTC®2605/LTC2615/LTC2625 are octal 16-, 14-
and 12-bit, 2.7V to 5.5V rail-to-rail voltage-output DACs in
16-lead narrow SSOP packages. They have built-in
high performance output buffers and are guaranteed
monotonic.
These parts establish new board-density benchmarks
for 16- and 14-bit DACs and advance performance
standards for output drive, crosstalk and load regulation
in single-supply, voltage-output multiples.
The parts use the 2-wire I2C compatible serial interface.
The LTC2605/LTC2615/LTC2625 operate in both the
standard mode (maximum clock rate of 100kHz) and the
fast mode (maximum clock rate of 400kHz).
The LTC2605/LTC2615/LTC2625 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise
less than 10mV above zero scale; and after power-up, they
stay at zero scale until a valid write and update take place.
The power-on reset circuit resets the LTC2605-1/
LTC2615-1/LTC2625-1 to midscale. The voltage output
stays at midscale until a valid write and update
takes place.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
BLOCK DIAGRA
GND 1
VOUT A 2
DAC A
VOUT B 3
DAC B
VOUT C 4
DAC C
VOUT D 5
REF 6
CA2 7
SCL 8
DAC D
32-BIT SHIFT REGISTER
2-WIRE INTERFACE
DAC H
16 VCC
15 VOUT H
DAC G
14 VOUT G
DAC F
13 VOUT F
DAC E
12 VOUT E
11 CA0
10 CA1
9 SDA
2605/15/25 BD
Differential Nonlinearity (LTC2605)
1.0
VCC = 5V
0.8 VREF = 4.096V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384
32768
CODE
49152 65535
2605 G02
2605f
1
1 page  
ELECTRICAL CHARACTERISTICS
Test Circuit 1
100Ω
CAn
VIH(CAn)/VIL(CAn)
2605/15/25 EC01
LTC2605/LTC2615/LTC2625
Test Circuit 2
VDD
RINH/RINL/RINF
2605/15/25 EC02
GND
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2605
Integal Nonlinearity (INL)
32
VCC = 5V
24 VREF = 4.096V
16
8
0
www.DataSheet4U.com –8
–16
–24
–32
0
16384
32768
CODE
49152 65535
2605 G01
Differential Nonlinearity (DNL)
1.0
VCC = 5V
0.8 VREF = 4.096V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384
32768
CODE
49152
65535
2605 G02
DNL vs Temperature
1.0
VCC = 5V
0.8 VREF = 4.096V
0.6
0.4
DNL (POS)
0.2
0
–0.2
DNL (NEG)
–0.4
–0.6
–0.8
–1.0
–50 –30 –10 10 30 50
TEMPERATURE (°C)
70 90
2605 G04
INL vs VREF
32
VCC = 5.5V
24
16
8 INL (POS)
0
–8 INL (NEG)
–16
–24
–32
0123
VREF (V)
45
2605 G05
INL vs Temperature
32
VCC = 5V
24 VREF = 4.096V
16
8 INL (POS)
0
–8
INL (NEG)
–16
–24
–32
–50 –30 –10 10 30 50
TEMPERATURE (°C)
70 90
2605 G03
DNL vs VREF
1.5
VCC = 5.5V
1.0
0.5
DNL (POS)
0
DNL (NEG)
–0.5
–1.0
–1.5
012345
VREF (V)
2605 G06
2605f
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5 Page 
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OPERATIO
LTC2605/LTC2615/LTC2625
WRITE WORD PROTOCOL FOR LTC2605/LTC2615/LTC2625
S SLAVE ADDRESS W A 1ST DATA BYTE A 2ND DATA BYTE A 3RD DATA BYTE A P
INPUT WORD
INPUT WORD (LTC2605)
C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1ST DATA BYTE
2ND DATA BYTE
3RD DATA BYTE
INPUT WORD (LTC2615)
C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
1ST DATA BYTE
2ND DATA BYTE
3RD DATA BYTE
INPUT WORD (LTC2625)
C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
1ST DATA BYTE
2ND DATA BYTE
3RD DATA BYTE 2605/2615/2625 O01
Figure 2
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge
relatedwww.DataSheet4U.com clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
during the Acknowledge clock pulse so that it remains a
stable LOW during the HIGH period of this clock pulse. The
LTC2605/LTC2615/LTC2625 respond to a write by a mas-
ter in this manner. The LTC2605/LTC2615/LTC2625 do
not acknowledge a read (it retains SDA HIGH during the
period of the Acknowledge clock pulse).
Chip Address
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set to
any one of three states: VCC, GND or FLOAT. This results
in 27 selectable addresses for the part. The addresses
corresponding to the states of CA0, CA1 and CA2 and the
global address are shown in Table 2.
In addition to the address selected by the address pins, the
parts also respond to a global address. This address allows
a common write to all LTC2605, LTC2615 and LTC2625
parts to be accomplished with one 3-byte write transaction
on the I2C bus. The global address is a 7-bit hardwired
address and is not selectable by CA0, CA1 and CA2. The
maximum capacitive load allowed on the address pins
(CA0, CA1 and CA2) is 10pF.
Write Word Protocol
The master initiates communication with the LTC2605/
LTC2615/LTC2625 with a START condition and a 7-bit
slave address followed by the Write bit (W) = 0. The
LTC2605/LTC2615/LTC2625 acknowledges by pulling the
SDA pin low at the 9th clock if the 7-bit slave address
matches the address of the parts (set by CA0, CA1 and
CA2) or the global address. The master then transmits
three bytes of data. The LTC2605/LTC2615/LTC2625
acknowledges each byte of data by pulling the SDA line low
at the 9th clock of each data byte transmission. After
receiving three complete bytes of data, the LTC2605/
LTC2615/LTC2625 executes the command specified in
the 24-bit input word.
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2605/LTC2615/LTC2625 do
not acknowledge the extra bytes of data (SDA is high
during the 9th clock).
The format of the three data bytes is shown in Figure 2. The first
byte of the input word consists of the 4-bit command and 4-
bit DAC address. The next two bytes consist of the 16-bit data
word. The 16-bit data word consists of the 16-, 14- or 12-bit
input code, MSB to LSB, followed by 0, 2 or 4 don’t care bits
(LTC2605, LTC2615 and LTC2625 respectively). A typical I2C
write transaction is shown in Figure 3.
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11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LTC2615.PDF ] | |
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