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PDF TSS461F Data sheet ( Hoja de datos )
| Número de pieza | TSS461F | |
| Descripción | VAN Data Link Controller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Fully Compliant to VAN Specification ISO/11519.3
• Handles All Specified Module Types
• Handles All Specified Message Types
• Handles Retransmission of Frames on Contention and Errors
• 3 Separate Line Inputs with Automatic Diagnosis and Selection
• 1 Mbit/s Maximum Transfer Rate
• Normal or Pulsed (Optical and Radio Mode) Coding
• Intel®, NEC®, Texas Instruments® and Motorola® Compatible 8-bit Microprocessor
Interface
• Multiplexed Address and Data Bus
• Idle and Sleep Modes
• 128 Bytes of General-purpose RAM
• DMA Capabilities for Message Handling
• 14 Identifier Registers with All Bits Individually Maskable
• 6-source Maskable Interrupt Including an Interrupt-on-reset to Detect Glitches on the
Reset Pin
• Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and
Buffered Clock Output
• Single +5V Power Supply
• 0.5 mm CMOS Technology
• SOP 24 Packaging
VAN Data Link
Controller
TSS461F
Description
Cost optimization in car manufacturing is of extreme importance today. Solutions to
this problem often implies the use of more advanced and intelligent electronic circuits.
The TSS461F is a circuit which allows the transfer of all the status information needed
in a carwww.DataSheet4U.com or truck over a single low-cost wire pair, thereby, minimizing the electrical wire
usage.
It can be used to interconnect powerful functions (ABS, dashboard, power train con-
trol) and to control and interface car body electronics (lights, wipers, power window,
etc.).
The TSS461F is fully compliant with the ISO standard 11519-3. This standard sup-
ports a wide range of applications such as low-cost remote control switches, typically
used for lamp control; complex, highly-autonomous, distributed systems like engine
controls, which require fast and secure data transfers.
The TSS461F is a microprocessor-interfaced line controller for mid-to-high complexity
bus-masters and listeners like injection/ignition control calculators, dashboard control-
lers and car stereo or mobile telephone CPUs.
The microprocessor interface consists of a 256-bytes of RAM and the register area is
divided into 11 control registers, 14 channel register sets and 128 bytes of general
purpose RAM, used as a message storage area, and a 6-source maskable interrupt.
The circuit operates in RAM using DMA techniques, controlled by the channel and
control registers. This allows virtually any microprocessor to interface with ease to the
TSS461F, and to use the free RAM as a scratch pad.
Messages are encoded in enhanced Manchester code, and an optional pulsed code
for use with an optical or radio link, at a maximum bit rate of 1 Mbit/s. The TSS461F
analyzes the messages received or transmitted according to 6 different criteria includ-
ing some higher level checks.
In addition, the bus interface has three separate inputs with automatic source diagno-
sis and selection, allowing for multibus listening or the automatic selection of the most
reliable source at any time if several line receivers are connected to the same bus.
7615A–AUTO–02/06
1 page  
TSS461F
Operation
The TSS461F is a microprocessor-controlled line controller for the VAN bus. It can interface to
virtually any microprocessor, but the I/O signals of the circuit have been optimized for use with
the TSC51/TSC251 series of microcontrollers.
It features a multiplexed address and data bus, controlled by an address strobe pin ALE and
separated read RD and write WR command pins. The address is latched on the falling edge of
ALE.
The circuit also features one single interrupt pin. This pin can be treated as level or edge sensi-
tive, For example, if there is a pending interrupt inside the circuit when another interrupt is reset,
the INT pin will emit a high pulse with the same pulse width as the internal write strobe (typically
20 ns).
Figure 2. Typical Application
VAN Bus
Remaining Pins
General I/O
TSS461F
Series
Microcontroller
C1 33 pF
GND XTAL1
XTAL2 GND
P3.6/WR
P3.7/RD
ALE
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
RESET XTAL1 INT
WR TXD
RD
RXD0
ALE
VAN RXD1
DLC RXD2
AD7
AD6
AD5
AD4
AD3
AD2
AD1
CS
AD0
VCC INT CKOUT RESET
Differential
+
-
DATA
+
-
VREF
DATA
+
-
VAN Line Driver
& Receivers
7615A–AUTO–02/06
5
5 Page 
VAN Protocol
Line Interface
TSS461F
There are three line inputs and one line output available on the TSS461F. Each of the three
inputs to use is either programmed by software or automatically selected by a diagnosis system.
The diagnosis system continuously monitors the data received through the three inputs, and
compares them and the selected bitrate. It then chooses the most reliable input according to the
results.
The data on the line is encoded according to the VAN standard ISO/11519-3. This means that
the TSS461F is using a two-level signal having a recessive (1) and a dominant (0) state. Fur-
thermore, due to the simple medium used, all data transmitted on the bus is also received
simultaneously.
Consequently, the VAN protocol is a CSMA/CD (Carrier Sense Multiple Access/Collision Detec-
tion) protocol, allowing for continuous bitwise arbitration of the bus, and non-destructive (for the
higher priority message) collision detection.
Figure 5. CSMA/CD Arbitration
Arbitration field
R
Node a: TxD D
R
Node b: TxD D
R
Node c: TxD D
R
On Bus: DATA D
2
Node a loses the arbitration
Node a releases the bus
3 Node b wins the arbitration
1 Node c loses the arbitration
Node c releases the bus
R: Recessive level
D: Dominant level
In addition to the VAN specification there is also a pulsed coding of the dominant and recessive
states. This mode is intended to be used with an optical or radio link. In this mode, the dominant
state for the transmitter is a low pulse, (2x prescaled clocks at the beginning of the bit) and the
recessive state is just a high level.
When receiving in this mode, it is not the state of the signal which is decoded, but the edges.
Also, reception is imposed on the RxD0 input, and the diagnosis system does not operate
correctly.
In addition, in this mode there is an internal loopback in the circuit since optical transceivers are
not able to receive the signal that they transmit.
7615A–AUTO–02/06
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TSS461F.PDF ] | |
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