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PDF MAX5064 Data sheet ( Hoja de datos )
| Número de pieza | MAX5064 | |
| Descripción | (MAX5062 - MAX5064) Half-Bridge MOSFET Drivers | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-3502; Rev 3; 10/05
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
General Description
The MAX5062/MAX5063/MAX5064 high-frequency,
125V half-bridge, n-channel MOSFET drivers drive high-
and low-side MOSFETs in high-voltage applications.
These drivers are independently controlled and their
35ns typical propagation delay, from input to output, are
matched to within 3ns (typ). The high-voltage operation
with very low and matched propagation delay between
drivers, and high source/sink current capabilities in a
thermally enhanced package make these devices suit-
able for the high-power, high-frequency telecom power
converters. The 125V maximum input voltage range pro-
vides plenty of margin over the 100V input transient
requirement of telecom standards. A reliable on-chip
bootstrap diode connected between VDD and BST elimi-
nates the need for an external discrete diode.
The MAX5062A/C and the MAX5063A/C offer both nonin-
verting drivers (see the Selector Guide). The
MAX5062B/D and the MAX5063B/D offer a noninverting
high-side driver and an inverting low-side driver. The
MAX5064A/B offer two inputs per driver that can be
either inverting or noninverting. The MAX5062A/B/C/D
and the MAX5064A feature CMOS (VDD / 2) logic inputs.
Thewww.DataSheet4U.com MAX5063A/B/C/D and the MAX5064B feature TTL
logic inputs. The MAX5064A/B include a break-before-
make adjustment input that sets the dead time between
drivers from 16ns to 95ns. The drivers are available in the
industry-standard 8-pin SO footprint and pin configura-
tion, and a thermally enhanced 8-pin SO and 12-pin
(4mm x 4mm) thin QFN packages. All devices operate
over the -40°C to +125°C automotive temperature range.
Applications
Telecom Half-Bridge Power Supplies
Two-Switch Forward Converters
Full-Bridge Converters
Active-Clamp Forward Converters
Power-Supply Modules
Motor Control
Features
♦ HIP2100/HIP2101 Pin Compatible (MAX5062A/
MAX5063A)
♦ Up to 125V Input Operation
♦ 8V to 12.6V VDD Input Voltage Range
♦ 2A Peak Source and Sink Current Drive Capability
♦ 35ns Typical Propagation Delay
♦ Guaranteed 8ns Propagation Delay Matching
Between Drivers
♦ Programmable Break-Before-Make Timing
(MAX5064)
♦ Up to 1MHz Combined Switching Frequency while
Driving 100nC Gate Charge (MAX5064)
♦ Available in CMOS (VDD / 2) or TTL Logic-Level
Inputs with Hysteresis
♦ Up to 15V Logic Inputs Independent of Input
Voltage
♦ Low 2.5pF Input Capacitance
♦ Instant Turn-Off of Drivers During Fault or PWM
Start-Stop Synchronization (MAX5064)
♦ Low 200µA Supply Current
♦ Versions Available With Combination of
Noninverting and Inverting Drivers (MAX5062B/D
and MAX5063B/D)
♦ Available in 8-Pin SO, Thermally Enhanced SO,
and 12-Pin Thin QFN Packages
Ordering Information
PART
TEMP RANGE
PIN-
TOP
PACKAGE MARK
PKG
CODE
MAX5062AASA -40°C to +125°C 8 SO
— S8-5
MAX5062BASA -40°C to +125°C 8 SO
— S8-5
MAX5062CASA -40°C to +125°C 8 SO-EP* — S8E-14
MAX5062DASA -40°C to +125°C 8 SO-EP* — S8E-14
*EP = Exposed paddle.
Ordering Information continued at end of data sheet.
Selector Guide
PART
HIGH-SIDE DRIVER
MAX5062AASA
Noninverting
MAX5062BASA
Noninverting
MAX5062CASA
Noninverting
MAX5062DASA
Noninverting
Selector Guide continued at end of data sheet.
LOW-SIDE DRIVER
Noninverting
Inverting
Noninverting
Inverting
LOGIC LEVELS
CMOS (VDD / 2)
CMOS (VDD / 2)
CMOS (VDD / 2)
CMOS (VDD / 2)
PIN COMPATIBLE
HIP 2100IB
—
—
—
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Typical Operating Characteristics
(Typical values are at VDD = VBST = +12V and TA = +25°C, unless otherwise specified.)
UNDERVOLTAGE LOCKOUT
(VDD AND VBST RISING) vs. TEMPERATURE
7.5
7.4
7.3 UVLOVDD
7.2
7.1
7.0
6.9 UVLOBST
6.8
6.7
6.6
6.5
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
VDD AND BST UNDERVOLTAGE LOCKOUT
HYSTERESIS vs. TEMPERATURE
1.0
0.9
0.8
0.7 UVLOVDD
0.6 HYSTERESIS
0.5
UVLOBST
0.4 HYSTERESIS
0.3
0.2
0.1
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2V/div
0V
500µA/div
0A
IDD vs. VDD
MAX5064
IN_L-, IN_H- = VDD
IN_L+, IN_H+ = GND
40µs/div
MAX5062/3/4 toc03
VDD
IDD
IDDO + IBSTO vs. VDD
(fSW = 250kHz)
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13
VDD (V)
VDD QUIESCENT CURRENT
vs. VDD (NO SWITCHING)
160
MAX5064
140
TA = +125°C
120
TA = +25°C, TA = 0°C
100
80
60
TA = -40°C
40
20
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VDD (V)
200
180
160
140
120
100
80
60
40
20
0
0.5
INTERNAL BST DIODE
(I-V) CHARACTERISTICS
TA = +125°C
TA = +25°C
TA = 0°C
TA = -40°C
0.6 0.7 0.8 0.9 1.0
VDD - VBST (V)
BST QUIESCENT CURRENT
vs. BST VOLTAGE
21
VBST = VDD + 1V,
18 NO SWITCHING
1.1
15
12 TA = +125°C
9
6
3
TA = -40°C, TA = 0°C, TA = +25°C
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VBST (V)
_______________________________________________________________________________________ 5
5 Page 
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
The voltage at BBM is regulated to 1.3V. The BBM circuit
adjusts tBBM depending on the current drawn by RBBM.
Bypass BBM to AGND with a 1nF or smaller ceramic
capacitor (CBBM) to avoid any effect of ground bounce
caused during switching. The charging time of CBBM
does not affect tBBM at turn-on because the BBM voltage
is stabilized before the UVLO clears the device turn-on.
Topologies like the two-switch forward converter, where
both high- and low-side switches are turned on and off
simultaneously, can have the BBM function disabled by
leaving BBM unconnected. When disabled, tBBM is typi-
cally 1ns.
Driver Logic Inputs (IN_H, IN_L, IN_H+,
IN_H-, IN_L+, IN_L-)
The MAX5062_/MAX5064A are CMOS (VDD / 2) logic-
input drivers while the MAX5063_/MAX5064B have TTL-
compatible logic inputs. The logic-input signals are
independent of VDD. For example, the IC can be pow-
ered by a 10V supply while the logic inputs are provid-
ed from a 12V CMOS logic. Also, the logic inputs are
protected against voltage spikes up to 15V, regardless
of the VDD voltage. The TTL and CMOS logic inputs
have 400mV and 1.6V hysteresis, respectively, to avoid
double pulsing during transition. The logic inputs are
high-impedance pins and should not be left floating.
The low 2.5pF input capacitance reduces loading and
increases switching speed. The noninverting inputs are
pulled down to GND and the inverting inputs are pulled
up to VDD internally using a 1MΩ resistor. The PWM
output from the controller must assume a proper state
while powering up the device. With the logic inputs
floating, the DH and DL outputs pull low as VDD rises
up above the UVLO threshold.
The MAX5064_ has two logic inputs per driver, which
provide greater flexibility in controlling the MOSFET.
Use IN_H+/IN_L+ for noninverting logic and IN_H-/
IN_L- for inverting logic operation. Connect
IN_H+/IN_L+ to VDD and IN_H-/IN_L- to GND if not
used. Alternatively, the unused input can be used as an
ON/OFF function. Use IN_+ for active-low and IN_- for
active-high shutdown logic.
Table 1. MAX5064_ Truth Table
IN_H+/IN_L+
Low
Low
High
High
IN_H-/IN_L-
Low
High
Low
High
DH/DL
Low
Low
High
Low
Applications Information
Supply Bypassing and Grounding
Pay extra attention to bypassing and grounding the
MAX5062/MAX5063/MAX5064. Peak supply and output
currents may exceed 4A when both drivers are driving
large external capacitive loads in-phase. Supply drops
and ground shifts create forms of negative feedback for
inverters and may degrade the delay and transition
times. Ground shifts due to insufficient device ground-
ing may also disturb other circuits sharing the same AC
ground return path. Any series inductance in the VDD,
DH, DL, and/or GND paths can cause oscillations due
to the very high di/dt when switching the MAX5062/
MAX5063/MAX5064 with any capacitive load. Place
one or more 0.1µF ceramic capacitors in parallel as
close to the device as possible to bypass VDD to GND
(MAX5062/MAX5063) or PGND (MAX5064). Use a
ground plane to minimize ground return resistance and
series inductance. Place the external MOSFET as close
as possible to the MAX5062/MAX5063/MAX5064 to fur-
ther minimize board inductance and AC path resis-
tance. For the MAX5064_ the low-power logic ground
(AGND) is separated from the high-power driver return
(PGND). Apply the logic-input signal between IN_ to
AGND and connect the load (MOSFET gate) between
DL and PGND.
Power Dissipation
Power dissipation in the MAX5062/MAX5063/MAX5064
is primarily due to power loss in the internal boost
diode and the nMOS and pMOS FETS.
For capacitive loads, the total power dissipation for the
device is:
( )PD
=
⎛
⎝
CL
×
VDD2 ×
fSW
⎞
⎠
+
IDDO +
IBSTO
× VDD
where CL is the combined capacitive load at DH and
DL. VDD is the supply voltage and fSW is the switching
frequency of the converter. PD includes the power dis-
sipated in the internal bootstrap diode. The internal
power dissipation reduces by PDIODE, if an external
bootstrap Schottky diode is used. The power dissipa-
tion in the internal boost diode (when driving a capaci-
tive load) will be the charge through the diode per
switching period multiplied by the maximum diode for-
ward voltage drop (Vf = 1V).
( )PDIODE = CDH × VDD − 1 × fSW × Vf
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet MAX5064.PDF ] | |
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