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PDF MAX1182 Data sheet ( Hoja de datos )

Número de pieza MAX1182
Descripción Low-Power ADC
Fabricantes Maxim Integrated Products 
Logotipo Maxim Integrated Products Logotipo



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19-2094; Rev 1; 4/06
Dual 10-Bit, 65Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
General Description
The MAX1182 is a 3V, dual 10-bit analog-to-digital con-
verter (ADC) featuring fully-differential wideband track-
and-hold (T/H) inputs, driving two pipelined, 9-stage
ADCs. The MAX1182 is optimized for low-power, high-
dynamic performance applications in imaging, instru-
mentation and digital communication applications. This
ADC operates from a single 2.7V to 3.6V supply, con-
suming only 195mW while delivering a typical signal-to-
noise ratio (SNR) of 59dB at an input frequency of
20MHz and a sampling rate of 65Msps. The T/H driven
input stages incorporate 400MHz (-3dB) input amplifiers.
The converters may also be operated with single-ended
inputs. In addition to low operating power, the MAX1182
features a 2.8mA sleep mode as well as a 1µA power-
down mode to conserve power during idle periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of the internal or an externally
derived reference, if desired for applications requiring
increased accuracy or a different input voltage range.
The MAX1182 features parallel, CMOS-compatible
three-state outputs. The digital output format is set to
two’swww.DataSheet4U.com complement or straight offset binary through a
single control pin. The device provides for a separate
output power supply of 1.7V to 3.6V for flexible interfac-
ing. The MAX1182 is available in a 7mm x 7mm, 48-pin
TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible higher and lower speed versions of the
MAX1182 are also available. Please refer to the
MAX1180 datasheet for 105Msps, the MAX1181
datasheet for 80Msps, the MAX1183 datasheet for
40Msps, and the MAX1184 datasheet for 20Msps. In
addition to these speed grades, this family includes a
20Msps multiplexed output version (MAX1185), for
which digital data is presented time-interleaved on a
single, parallel 10-bit output port.
Applications
High Resolution Imaging
I/Q Channel Digitization
Multchannel IF Undersampling
Instrumentation
Video Application
Features
o Single 3V Operation
o Excellent Dynamic Performance:
59dB SNR at fIN = 20MHz
77dB SFDR at fIN = 20MHz
o Low Power:
65mA (Normal Operation)
2.8mA (Sleep Mode)
1µA (Shutdown Mode)
o 0.02dB Gain and 0.25° Phase Matching (typ)
o Wide ±1VP-P Differential Analog Input Voltage
Range
o 400MHz -3dB Input Bandwidth
o On-Chip 2.048V Precision Bandgap Reference
o User-Selectable Output Format—Two’s
Complement or Offset Binary
o 48-Pin TQFP Package with Exposed Pad for
Improved Thermal Dissipation
o Evaluation Kit Available
Ordering Information
PART
TEMP RANGE
PIN-
PACKAGE
PKG
CODE
MAX1182ECM -40°C to +85°C 48 TQFP-EP* C48E-7
MAX1182ECM+ -40°C to +85°C 48 TQFP-EP* C48E-7
+Denotes lead-free package.
*EP = Exposed paddle.
Pin-Compatible Versions table at end of data sheet.
Pin Configuration
COM 1
VDD 2
GND 3
INA+ 4
INA- 5
VDD 6
GND 7
INB- 8
INB+ 9
GND 10
VDD 11
CLK 12
MAX1182
EP
36 D1A
35 D0A
34 OGND
33 OVDD
32 OVDD
31 OGND
30 D0B
29 D1B
28 D2B
27 D3B
26 D4B
25 D5B
48 TQFP-EP
NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE
PACKAGES IS REPLACED BY A "+" SIGN.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX1182 pdf
Dual 10-Bit, 65Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kresistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 1), fCLK = 65MHz (50% duty cycle),
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
VDD
OVDD
IVDD
Operating, fINA or B = 20MHz at -0.5dBFS
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
2.7 3.0 3.6
V
1.7 2.5 3.6
V
65 80
mA
2.8
1 15 µA
Output Supply Current
IOVDD
Operating, CL = 15pF,
fINA or B = 20MHz at -0.5dBFS
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
11 mA
100
2 10
µA
Power Dissipation
Power-Supply Rejection Ratio
PDISS
PSRR
Operating, fINA or B = 20MHz at -0.5dBFS
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
Offset
Gain
195 240
mW
8.4
3 45 µW
±0.2 mV/V
±0.1 %/V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
tDO Figure 3 (Note 5)
5 8 ns
Output Enable Time
tENABLE Figure 4
10 ns
Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
tDISABLE
tCH
tCL
Figure 4
Figure 3, clock period: 15.4ns
Figure 3, clock period: 15.4ns
1.5
7.7 ± 1.5
7.7 ± 1.5
ns
ns
ns
Wake-Up Time
tWAKE
Wake-up from sleep mode (Note 6)
Wake-up from shutdown (Note 6)
0.42
µs
1.5
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
fINA or B = 20MHz at -0.5dBFS
-70 dB
Gain Matching
Phase Matching
fINA or B = 20MHz at -0.5dBFS
fINA or B = 20MHz at -0.5dBFS
0.02 ±0.2 dB
0.25 degrees
Note 1: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL.
Note 2: Specifications at +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a ±1.024V full-scale
input voltage range.
Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 5: Digital outputs settle to VIH, VIL. Parameter guaranteed by design.
Note 6: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
_______________________________________________________________________________________ 5

5 Page





MAX1182 arduino
Dual 10-Bit, 65Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Detailed Description
The MAX1182 uses a 9-stage, fully-differential
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
Counting the delay through the output latch, the clock-
cycle latency is five clock cycles.
1.5-bit (2-comparator) flash ADCs convert the held-
input voltages into a digital code. The digital-to-analog
converters (DACs) convert the digitized results back
into analog voltages, which are then subtracted from
the original held input signals. The resulting error sig-
nals are then multiplied by two and the residues are
passed along to the next pipeline stages where the
process is repeated until the signals have been
processed by all nine stages. Digital error correction
compensates for ADC comparator offsets in each of
these pipeline stages and ensures no missing codes.
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track and
hold mode. In track mode, switches S1, S2a, S2b, S4a,
S4b, S5a and S5b are closed. The fully-differential cir-
cuits sample the input signals onto the two capacitors
(C2a and C2b) through switches S4a and S4b. S2a and
S2b set the common mode for the amplifier input, and
open simultaneously with S1, sampling the input wave-
form. Switches S4a and S4b are then opened before
switches S3a and S3b, connect capacitors C1a and
C1b to the output of the amplifier, and switch S4c is
closed. The resulting differential voltages are held on
capacitors C2a and C2b. The amplifiers are used to
charge capacitors C1a and C1b to the same values
originally held on C2a and C2b. These values are then
presented to the first-stage quantizers and isolate the
pipelines from the fast-changing inputs. The wide input
bandwidth T/H amplifiers allow the MAX1182 to track-
and-sample/hold analog inputs of high frequencies (>
Nyquist). The ADC inputs (INA+, INB+, INA-, and INB-)
can be driven either differentially or single-ended.
Match the impedance of INA+ and INA- as well as
INB+ and INB- and set the common-mode voltage to
mid-supply (VDD / 2) for optimum performance.
VIN T/H Σ x2 VOUT
VIN T/H Σ x2 VOUT
FLASH
ADC
DAC
1.5 BITS
STAGE 1
STAGE 2
STAGE 8
2-BIT FLASH
ADC
STAGE 9
FLASH
ADC
DAC
1.5 BITS
STAGE 1
STAGE 2
STAGE 8
2-BIT FLASH
ADC
STAGE 9
T/H
VINA
DIGITAL CORRECTION LOGIC
10
DIGITAL CORRECTION LOGIC
T/H 10
D9A–D0A
VINB
VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE-ENDED)
VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE-ENDED)
D9B–D0B
Figure 1. Pipelined Architecture—Stage Blocks
______________________________________________________________________________________ 11

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