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PDF ISL54103 Data sheet ( Hoja de datos )
| Número de pieza | ISL54103 | |
| Descripción | DDC Accelerator | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
PRELIMINARY
Data Sheet
June 22, 2006
ISL54103
FN6303.1
DDC Accelerator (DDCA)
The ISL54103 DDC Accelerator (DDCA) is a dual active
pull-up bus terminator designed to improve data
transmission speed on the DDC 2-wire serial bus interfaces.
The DDCA detects rising input transitions with two internal
voltage references and two comparators per channel. After
the voltage on a data line crosses the first threshold
(VTRIPL), the boost pull-up current source is activated to
speed transition. After the voltage crosses the second
threshold (VTRIPH), the boost pull-up current source is
de-activated, leaving an active pull-up current of 275µA on
the line. When both channels are HIGH, the pull-up current
for both lines is reduced to 100µA to save power. Internal
logic ensures that the active and boost pull-up current
sources are not activated during downward transitions.
The level for VTRIPH is controlled by a bandgap voltage
referred to VDD. This feature makes the switching behavior
invariant for all power supply voltages between 2.7V and
5.5V.
A noise filter on each channel prevents the circuit from
responding to input transitions that do not exceed a
www.DataSheet4U.covmoltage-time threshold. To activate the boost circuit, the input
must exceed VTRIPL by 100Vns (typical) (See Figure 10).
The DDCA permits operation of the bus at frequencies up to
100kHz, despite the capacitive loads of multiple devices
and/or long PC board traces. Enhanced ESD protection on
the accelerator pins are guaranteed to withstand 8kV ESD
(HBM) events.
The DDC Accelerator provides an essential function in DDC
applications because of distributed capacitance of the DDC
wires in long video cables. By incorporating DDCA, systems
using DDC can reliably increase their bus load, allowing
longer cables, without the risk of data corruption.
Ordering Information
PART NUMBER
TAPE & TEMP RANGE
REEL
(°C)
PACKAGE
ISL54103IHZ-T7
(Note)
7” -40 to 85 5 Ld SOT-23
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• Active Termination for DDC Lines
• Enhances System Bus Signal Rise Time
• More Reliable HDCP Performance In Video Multiplexers
and Cable Extenders
• Increases Maximum Cable Length While Guaranteeing
Data Integrity
• 2.2mA Current Boost on Low to High Transitions
• 8kV ESD Protection on SDA and SCL Pins
• Wide Operating Voltage Range: 2.7V to 5.5V
• Small Package - 5 Ld SOT-23
• Pb-free Plus Anneal Available (RoHS Compliant)
Target Applications
• Video Multiplexers
• Video Cable Extenders
• Video Distribution Amplifiers
• Televisions
• Computer Monitors
• Projectors
Pinout
ISL54103
(5 LD SOT-23)
TOP VIEW
VDD
GND
N.C.
1
2
3
5 DDC1
4 DDC2
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL54103
Typical Performance Curves (Continued)
0.70
0.65
0.60
0.55
0.50
0.45
VDD = 5.5V
VDD = 2.7V
0.40
0.35
0.30
-60 -40 -20 0 20 40 60
TEMPERATURE (°C)
80 100
FIGURE 5. VTRIPH VOLTAGE
95
90
85
VDD = 5.5V
80
75 VDD = 2.7V
70
65
60
55
-60 -40 -20 0 20 40 60
TEMPERATURE (°C)
80 100
FIGURE 6. IDD CURRENT, DDC1 = DDC2 = OPEN
3.5
3.0
2.5
VDD = 5.0V
2.0
1.5
VDD = 2.7V
1.0
0.5
0
0123456
DDC VOLTAGE (V)
FIGURE 7. BOOST PULL-UP CURRENT vs DDC VOLTAGE
Functional Description
DDC Overview
DDC is a 2-wire serial communication standard based on the
I2C standard. Devices communicate to each other using one
clock (SCL) and one data (SDA) line. These are both
bidirectional.
Each signal is connected to a positive supply voltage via a
current-source or pull-up resistor (see “System Diagram” on
page 2). When the bus is free, both lines are HIGH. The
output stages of all devices connected to the bus must have
an open-drain or open-collector to perform the wired-AND
function.
Simple pull-up resistors on the clock and data lines work well
unless there are long signal lines. The combined
capacitance of long cables increases the rise time on the
signal to such an extent that the communication becomes
unreliable or fails to meet the bus timing specifications.
Smaller value resistors can sometimes compensate for the
extra capacitance, but this increases the current
consumption when the signal lines are pulled LOW.
ISL54103 Operation
To improve the operation of the DDC where larger bus
capacitance exists, the ISL54103 provides active pull-up
using switched current sources. When the bus is idle and
both lines are HIGH, a standby pull-up current of 100µA is
used to maintain the signal level while minimizing power
5 FN6303.1
June 22, 2006
5 Page | ||
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| PDF Descargar | [ Datasheet ISL54103.PDF ] | |
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