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PDF LT1168 Data sheet ( Hoja de datos )
| Número de pieza | LT1168 | |
| Descripción | Precision Instrumentation Amplifier | |
| Fabricantes | Linear Technology | |
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LT1168
FEATURES
Low Power, Single
Resistor Gain Programmable,
Precision Instrumentation Amplifier
DESCRIPTIO
■ Supply Current: 530µA Max
■ Meets IEC 1000-4-2 Level 4 (±15kV) ESD Tests
with Two External 5k Resistors
■ Single Gain Set Resistor: G = 1 to 10,000
■ Gain Error: G = 10, 0.4% Max
■ Input Offset Voltage Drift: 0.3µV/°C Max
■ Gain Nonlinearity: G = 10, 20ppm Max
■ Input Offset Voltage: 40µV Max
■ Input Bias Current: 250pA Max
■ PSRR at AV =1: 103dB Min
■ CMRR at AV = 1: 90dB Min
■ Wide Supply Range: ±2.3V to ±18V
■ 1kHz Voltage Noise: 10nV/√Hz
■ 0.1Hz to 10Hz Noise: 0.28µVP-P
■ Available in 8-Pin PDIP and SO Packages
U
APPLICATIO S
■ Bridge Amplifiers
■ Strain Gauge Amplifiers
■ Thermocouple Amplifiers
■ Differential to Single-Ended Converters
■ Differential Voltage to Current Converters
■ Data Acquisition
■ Battery-Powered and Portable Equipment
■ Medical Instrumentation
■ Scales
The LT ®1168 is a micropower, precision instrumentation am-
plifier that requires only one external resistor to set gains of
1 to 10,000. The low voltage noise of 10nV/√Hz (at 1kHz) is
not compromised by low power dissipation (350µA typical for
±15Vsupplies).Thewidesupplyrangeof±2.3Vto±18Vallows
the LT1168 to fit into a wide variety of industrial as well as
battery-powered applications.
The high accuracy of the LT1168 is due to a 20ppm maximum
nonlinearityand0.4%maxgainerror(G=10).Previousmono-
lithic instrumentation amps cannot handle a 2k load resistor
whereas the nonlinearity of the LT1168 is specified for loads
as low as 2k. The LT1168 is laser trimmed for very low input
offsetvoltage(40µVmax),drift(0.3µV/°C),highCMRR(90dB,
G = 1) and PSRR (103dB, G = 1). Low input bias currents of
250pA max are achieved with the use of superbeta process-
ing. The output can handle capacitive loads up to 1000pF in
any gain configuration while the inputs are ESD protected up
to 13kV (human body). The LT1168 with two external 5k
resistors passes the IEC 1000-4-2 level 4 specification.
The LT1168 is a pin-for-pin improved second source for the
AD620 and INA118. The LT1168, offered in 8-pin PDIP and
SO packages, requires significantly less PC board area than
discrete op amp resistor designs. These advantages make
the LT1168 the most cost effective solution for precision
instrumentation amplifier applications.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
Single Supply* Pressure Monitor
BI TECHNOLOGIES
5V 67-8-3 R40KQ, (0.02% RATIO MATCH)
Gain Nonlinearity
1 3+
87
40k
3.5k 3.5k
R1
G = 200
LT1168
6
249Ω
3.5k 3.5k
1
5
2– 4
20k
3+
1/2
1
40k LT1112
2–
*See Theory of Operation section
REF
IN
ADC
LTC®1286
DIGITAL
DATA
OUTPUT
AGND
1168 TA01
G = 1000
RL = 2k
VOUT = ±10V
OUTPUT VOLTAGE (2V/DIV)
1168 TA01a
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1
1 page  
LT1168
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the –40°C ≤ TA ≤ 85°C
temperature range. VS = ±15V, VCM = 0V, RL = 10k unless otherwise noted. (Note 5)
SYMBOL PARAMETER
CONDITIONS (Note 6)
LT1168AI
MIN TYP MAX
LT1168I
MIN TYP MAX
UNITS
VOST
VOSI
VOSIH
VOSO
VOSOH
VOSI/T
VOSO/T
IOS
IOS/T
IB
IB/T
VCM
CMRR
Total Input Referred Offset Voltage VOST = VOSI + VOSO/G
Input Offset Voltage
Input Offset Voltage Hysteresis (Notes 7, 10)
Output Offset Voltage
Output Offset Voltage Hysteresis (Notes 7, 10)
Input Offset Drift (RTI)
(Note 9)
Output Offset Drift
(Note 9)
Input Offset Current
Input Offset Current Drift
Input Bias Current
Input Bias Current Drift
Input Voltage Range
Common Mode
Rejection Ratio
VS = ±2.3V to ±5V
VS = ±5V to ±18V
1k Source Imbalance,
VCM = 0V to ±10V
G=1
G = 10
G = 100
G = 1000
● 20 75
25 100
● 3.0
3.0
● 180 500
200 600
● 30
30
● 0.05 0.3
0.06 0.4
● 0.8 5
16
● 110 550
120 700
● 0.3
0.3
● 120 500
220 800
● 1.4
1.4
● –VS + 2.1
● –VS + 2.1
+VS – 1.3 –VS + 2.1
+VS – 1.4 –VS + 2.1
+VS – 1.3
+VS – 1.4
µV
µV
µV
µV
µV/°C
µV/°C
pA
pA/°C
pA
pA/°C
V
V
● 86 90
● 98 105
● 114 118
● 116 133
81 90
95 105
112 118
112 133
dB
dB
dB
dB
PSRR
Power Supply
Rejection Ratio
VS = ±2.3V to ±18V
G=1
G = 10
G = 100
G = 1000
● 100 112
● 120 125
● 125 132
● 128 140
95 112
115 125
120 132
125 140
dB
dB
dB
dB
IS Supply Current
VOUT Output Voltage Swing
IOUT Output Current
SR Slew Rate
VS = ±2.3V to ±5V
VS = ±5V to ±18V
● 420 650
420 650
● –VS + 1.4
● –VS + 1.6
+VS – 1.3 –VS + 1.4
+VS – 1.5 –VS + 1.6
+VS – 1.3
+VS – 1.5
● 15 22
15 22
● 0.22 0.41
0.22 0.42
µA
V
V
mA
V/µs
VREF Voltage Range
(Note 9)
● –VS + 1.6
+VS – 1.6 –VS + 1.6
+VS – 1.6
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: If the input voltage exceeds the supplies, the input current should
be limited to less than 20mA.
Note 3: A heat sink may be required to keep the junction temperature
below absolute maximum.
Note 4: The LT1168AC/LT1168C are guaranteed functional over the
operating temperature range of – 40°C and 85°C.
Note 5: The LT1168AC/LT1168C are guaranteed to meet specified
performance from 0°C to 70°C. The LT1168AC/LT1168C are designed,
characterized and expected to meet specified performance from – 40°C
to 85°C but are not tested or QA sampled at these temperatures. The
LT1168AI/LT1168I are guaranteed to meet specified performance from
– 40°C to 85°C.
Note 6: Typical parameters are defined as the 60% of the yield parameter
distribution.
Note 7: Does not include the tolerance of the external gain resistor RG.
Note 8: This parameter is measured in a high speed automatic tester that
does not measure the thermal effects with longer time constants. The
magnitude of these thermal effects are dependent on the package used,
heat sinking and air flow conditions.
Note 9: This parameter is not 100% tested.
Note 10: Hysteresis in offset voltage is created by package stress that
differs depending on whether the IC was previously at a higher or lower
temperature. Offset voltage hysteresis is always measured at 25°C, but
the IC is cycled to 85°C I-grade (or 70°C C-grade) or – 40°C I-grade
(0°C C-grade) before successive measurement. 60% of the parts will
pass the typical limit on the data sheet.
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5
5 Page 
BLOCK DIAGRA
LT1168
+VS
–IN 2
R3
400Ω
–VS
RG 1
RG 8
+VS
+IN 3
R4
400Ω
–VS
VB
+
A1
–
C1
Q1
R1
24.7k
VB
+
A2
–
C2
Q2
R2
24.7k
PREAMP STAGE
R5 R6
30k 30k
6 OUTPUT
–
A3
+
–VS
R7 R8
30k 30k
5 REF
–VS
DIFFERENCE AMPLIFIER STAGE
7 +VS
4 –VS
1168 F01
Figure 1. Block Diagram
U
THEORY OF OPERATIO
The LT1168 is a modified version of the three op amp
instrumentation amplifier. Laser trimming and monolithic
construction allow tight matching and tracking of circuit
parameters over the specified temperature range. Refer to
the block diagram (Figure 1) to understand the following
circuit description. The collector currents in Q1 and Q2 are
trimmed to minimize offset voltage drift, thus assuring a
high level of performance. R1 and R2 are trimmed to an
absolute value of 24.7k to assure that the gain can be set
accurately (0.6% at G = 100) with only one external
resistor RG. The value of RG in parallel with R1 (R2)
determines the transconductance of the preamp stage. As
RG is reduced for larger programmed gains, the transcon-
ductance of the input preamp stage increases to that of the
input transistors Q1 and Q2. This increases the open-loop
gain when the programmed gain is increased, reducing
the input referred gain related errors and noise. The input
voltage noise at gains greater than 50 is determined only
by Q1 and Q2. At lower gains the noise of the difference
amplifier and preamp gain setting resistors increase the
noise. The gain bandwidth product is determined by C1,
C2 and the preamp transconductance which increases
with programmed gain. Therefore, the bandwidth does not
drop proportionally with gain.
The input transistors Q1 and Q2 offer excellent matching,
which is inherent in NPN bipolar transistors, as well as
picoampere input bias current due to superbeta process-
ing. The collector currents in Q1 and Q2 are held constant
due to the feedback through the Q1-A1-R1 loop and
Q2-A2-R2 loop which in turn impresses the differential
input voltage across the external gain set resistor RG.
Since the current that flows through RG also flows through
R1 and R2, the ratios provide a gained-up differential
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11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LT1168.PDF ] | |
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