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PDF CS51313 Data sheet ( Hoja de datos )
| Número de pieza | CS51313 | |
| Descripción | Synchronous CPU Buck Controller Capable of Implementing Multiple Linear Regulators | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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CS51313
Synchronous CPU
Buck Controller Capable
of Implementing Multiple
Linear Regulators
The CS51313 is a synchronous dual NFET Buck Regulator
Controller. It is designed to power the core logic of the latest high
performance CPUs. It uses the V2™ control method to achieve the
fastest possible transient response and best overall regulation. It
incorporates many additional features required to ensure the proper
operation and protection of the CPU and Power system. The CS51313
provides the industry’s most highly integrated solution, minimizing
external component count, total solution size, and cost.
The CS51313 is specifically designed to power Intel’s Pentium® II
processor and includes the following features: 5−bit DAC with 1.2%
tolerance, Power Good output, overcurrent hiccup mode protection,
overvoltage protection, VCC monitor, Soft Start, adaptive voltage
positioning and adaptive FET non−overlap time. A precision reference
trimmed to 1.0% is also externally available for use by other
regulators. The CS51313 will operate over an 8.4 V to 14 V range and
is available in 16 lead narrow body surface mount package.
Features
• Synchronous Switching Regulator Controller for CPU VCORE
• Dual N−Channel MOSFET Synchronous Buck Design
• V2 Control Topology
• 200 ns Transient Loop Response
• 5−Bit DAC with 1.2% Tolerance
• Hiccup Mode Overcurrent Protection
• 40 ns Gate Rise and Fall Times (3.3 nF Load)
• 65 ns Adaptive FET Non−Overlap Time
• Adaptive Voltage Positioning
• Power Good Output Monitors Regulator Output
• VCC Monitor Provides Undervoltage Lockout
• OVP Output Monitors Regulator Output
• Enable Through Use of the COMP Pin
• +1.23 V Reference Voltage Available Externally
http://onsemi.com
16
1
SO−16
D SUFFIX
CASE 751B
MARKING DIAGRAM
16
CS51313
AWLYWW
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
PIN CONNECTIONS
1
VID0
VID1
VID2
VID3
VREF
VID4
VFB
VOUT
16 COMP
COFF
PWRGD
OVP
GATE(L)
GND
GATE(H)
VCC
ORDERING INFORMATION
Device
Package
Shipping
CS51313GD16
SO−16
48 Units/Rail
CS51313GDR16
SO−16 2500 Tape & Reel
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 8
1
Publication Order Number:
CS51313/D
1 page  
CS51313
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCC < 14 V;
2.0 V DAC Code (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1.0) CGATE(H) = CGATE(L) = 3.3 nF, COFF = 390 pF; unless otherwise specified.)
Characteristic
Test Conditions
Min Typ Max Unit
Voltage Identification DAC (continued)
Line Regulation
Input Threshold
Input Pull−Up Resistance
Pull−Up Voltage
9.0 V ≤ VCC ≤ 14 V
VID4, VID3, VID2, VID1, VID0
VID4, VID3, VID2, VID1, VID0
−
− 0.01 − %/V
1.0 1.25 2.4
V
25 50 100 kΩ
5.48 5.65 5.82
V
Error Amplifier
VFB Bias Current
COMP Source Current
COMP Sink Current
Open Loop Gain
Unity Gain Bandwidth
PSRR @ 1.0 kHz
Transconductance
0.2 V ≤ VFB ≤ 3.5 V
VCOMP = 1.2 V to 3.6 V, VFB = 1.9 V
VCOMP = 1.2 V, VFB = 2.1 V
CCOMP = 0.1 μF
CCOMP = 0.1 μF
CCOMP = 0.1 μF
−
−7.0 0.1
7.0 μA
15 30 60 μA
30 60 120 μA
− 80 − dB
− 50 − kHz
− 70 − dB
− 32 − mmho
Output Impedance
− − 0.5 − MΩ
Bandgap Reference Voltage
VREF
GATE(H) and GATE(L)
IVREF = 10 μA Sourcing, VCC = 12 V
1.211 1.23 1.248
V
High Voltage at 100 mA
Low Voltage at 100 mA
Measure VCC − GATE(L)/(H)
Measure GATE(L)/(H)
− 1.2 2.1 V
− 1.0 1.5 V
Rise Time
Fall Time
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
GATE Pull−Down
1.6 V < GATE(H)/(L) < (VCC − 2.5 V)
(VCC − 2.5 V) > GATE(L)/(H) > 1.6 V
GATE(H) < 2.0 V, GATE(L) > 2.0 V, VCC = 12 V
GATE(L) < 2.0 V, GATE(H) > 2.0 V, VCC = 12 V
Resistance to GND. Note 4
−
−
30
30
20
40 80 ns
40 80 ns
65 110 ns
65 110 ns
50 115 kΩ
Overcurrent Protection
OVC Comparator Offset Voltage
Discharge Threshold Voltage
0 V ≤ VOUT ≤ 3.5 V
−
77 86 101 mV
0.2 0.25 0.3
V
VOUT Bias Current
OVC Latch Discharge Current
PWM Comparator
0.2 V ≤ VOUT ≤ 3.5 V
VCOMP = 1.0 V
−7.0 0.1
7.0 μA
100 800 2500 μA
PWM Comparator Offset Voltage
Transient Response
COFF
Off−Time
0 V ≤ VFB ≤ 3.5 V
VFB = 0 to 3.5 V
−
0.99 1.1 1.23 V
− 200 300 ns
1.0 1.6 2.3 μs
Charge Current
VCOFF = 1.5 V
Discharge Current
VCOFF = 1.5 V
4. Guaranteed by design, not 100% tested in production.
− 550 − μA
− 25 − mA
http://onsemi.com
5
5 Page 
CS51313
regulator output voltage will follow it, less the 1.1 V PWM
offset, until it achieves the voltage programmed by the
DAC’s VID input. The Error Amp will then source or sink
current to the COMP cap as required to maintain the correct
regulator DC output voltage. Since the rate of increase of the
COMP pin voltage is typically set much slower than the
regulator’s slew capability, inrush current, output voltage,
and duty cycle all gradually increase from zero. (See Figures
10, 11, and 12).
Channel 1 − Regulator Output Voltage (1.0 V/div)
Channel 2 − COMP Pin (1.0 V/div)
Channel 3 − VCC (10 V/div)
Channel 4 − Regulator Input Voltage (5.0 V/div)
Figure 10. Normal Startup (2.0 ms/div)
Channel 1 − Regulator Output Voltage (0.2 V/div)
Channel 2 − Inductor Switching Node (5.0 V/div)
Channel 3 − VCC (10 V/div)
Channel 4 − Regulator Input Voltage (5.0 V/div)
Figure 12. Pulse−By−Pulse Regulation During Soft
Start (2.0 ms/div)
If the voltage across the Current Sense resistor generates a
voltage difference between the VFB and VOUT pins that
exceeds the OVC Comparator Offset Voltage (86 mV typical),
the Fault latch is set. This causes the COMP pin to be quickly
discharged, turning off GATE(H) and the upper NFET since
the voltage on the COMP pin is now less than the 1.1 V PWM
comparator offset. The Fault latch is reset when the voltage on
the COMP decreases below the discharge threshold voltage
(0.25 V typical). The COMP capacitor will again begin to
charge, and when it exceeds the 1.1 V PWM comparator offset,
the regulator output will Soft Start normally (see Figure 13).
Channel 1 − Regulator Output Voltage (0.2 V/div)
Channel 2 − Inductor Switching Node (5.0 V/div)
Channel 3 − VCC (10 V/div)
Channel 4 − Regulator Input Voltage (5.0 V/div)
Figure 11. Normal Startup Showing Initial Pulse
Followed by Soft Start (20 ms/div)
http://onsemi.com
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet CS51313.PDF ] | |
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