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PDF A3988 Data sheet ( Hoja de datos )
| Número de pieza | A3988 | |
| Descripción | Quad DMOS Full Bridge PWM Motor Driver | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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A3988
Quad DMOS Full Bridge PWM Motor Driver
Features and Benefits
▪ 36 V output rating
▪ 4 full bridges
▪ Dual stepper motor driver
▪ High current outputs
▪ 3.3 and 5 V compatible logic supply
▪ Synchronous rectification
▪ Internal undervoltage lockout (UVLO)
▪ Thermal shutdown circuitry
▪ Crossover-current protection
▪ Low profile QFN package
Packages
Package EV, 36 pin QFN
0.90 mm nominal height
with exposed thermal pad
Package JP, 48 pin LQFP
with exposed thermal pad
Approximate scale
Description
The A3988 is a quad DMOS full-bridge driver capable of
driving up to two stepper motors or four dc motors. Each
full-bridge output is rated up to 1.2 A and 36 V. The A3988
includes fixed off-time pulse width modulation (PWM) current
regulators, along with 2- bit nonlinear DACs (digital-to-analog
converters) that allow stepper motors to be controlled in full,
half, and quarter steps, and dc motors in forward, reverse, and
coast modes. The PWM current regulator uses the Allegro®
patented mixed decay mode for reduced audible motor noise,
increased step accuracy, and reduced power dissipation.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation.
Protection features include thermal shutdown with hysteresis,
undervoltage lockout (UVLO) and crossover current protection.
Special power up sequencing is not required.
The A3988 is supplied in two packages, EV and JP, with
exposed power tabs for enhanced thermal performance. The
EV is a 6 mm x 6 mm, 36 pin QFN package with a nominal
overall package height of 0.90 mm. The JP is a 7 mm × 7 mm
48 pin LQFP. Both packages are lead (Pb) free, with 100%
matte tin leadframe plating.
A3988DS, Rev.3
Microprocessor
VREF
VDD 3.3 V
0.1 μF
50 V
0.1 μF
50 V
100 μF
50 V
VMOTOR 32 V
0.22 μF
50 V
PHASE1
I01
I11
PHASE2
I02
I12
PHASE3
I03
I13
PHASE4
I04
I14
VREF1
VREF2
VREF3
VREF4
VDD
A3988
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B
SENSE2
SENSE1
SENSE3
SENSE4
Bipolar Stepper Motors
RS2
RS1
RS3
RS4
Figure 1. Typical application circuit
1 page  
A3988
Quad DMOS Full Bridge PWM Motor Driver
Functional Description
Device Operation The A3988 is designed to operate two
stepper motors, four dc motors, or one stepper and two dc motors.
The currents in each of the output full-bridges, all N-channel
DMOS, are regulated with fixed off-time pulse width modulated
(PWM) control circuitry. Each full-bridge peak current is set by
the value of an external current sense resistor, RSx , and a refer-
ence voltage, VREFx .
If the logic inputs are pulled up to VDD, it is good practice to use
a high value pull-up resistor in order to limit current to the logic
inputs, should an overvoltage event occur. Logic inputs include:
PHASEx, I0x, and I1x.
Internal PWM Current Control Each full-bridge is con-
trolled by a fixed off-time PWM current control circuit that limits
the load current to a desired value, ITRIP. Initially, a diagonal pair
of source and sink DMOS outputs are enabled and current flows
through the motor winding and RSx. When the voltage across the
current sense resistor equals the voltage on the VREFx pin, the
current sense comparator resets the PWM latch, which turns off
the source driver.
The maximum value of current limiting is set by the selection of
RS and the voltage at the VREF input with a transconductance
function approximated by:
ITripMax = VREF / (3×RS)
Each current step is a percentage of the maximum current,
ITripMax. The actual current at each step ITrip is approximated by:
ITrip = (% ITripMax / 100) ITripMax
where % ITripMax is given in the Step Sequencing table.
Note: It is critical to ensure that the maximum rating of ±500 mV
on each SENSEx pin is not exceeded.
Fixed Off-Time The internal PWM current control circuitry
uses a one shot circuit to control the time the drivers remain off.
The one shot off-time, toff, is internally set to 30 μs.
Blanking This function blanks the output of the current sense
comparator when the outputs are switched by the internal current
control circuitry. The comparator output is blanked to prevent
false detections of overcurrent conditions, due to reverse recovery
currents of the clamp diodes, or to switching transients related to
the capacitance of the load. The stepper blank time, tBLANK , is
approximately 1 μs.
Control Logic Communication is implemented via the indus-
try standard I1, I0, and PHASE interface. This communication
logic allows for full, half, and quarter step modes. Each bridge
also has an independent VREF input so higher resolution step
modes can be programmed by dynamically changing the voltage
on the VREFx pins.
Charge Pump (CP1 and CP2) The charge pump is used to
generate a gate supply greater than the VBB in order to drive the
source-side DMOS gates. A 0.1 μF ceramic capacitor should be
connected between CP1 and CP2 for pumping purposes. A 0.1 μF
ceramic capacitor is required between VCP and VBBx to act as a
reservoir to operate the high-side DMOS devices.
Shutdown In the event of a fault (excessive junction tem-
perature, or low voltage on VCP), the outputs of the device are
disabled until the fault condition is removed. At power-up, the
undervoltage lockout (UVLO) circuit disables the drivers.
Allegro MicroSystems, Inc.
5
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5 Page 
A3988
Quad DMOS Full Bridge PWM Motor Driver
Package EV
I12 28
I11 29
GND 30
VCP 31
CP1 32
CP2 33
I01 34
I02 35
I03 36
Pin-out Diagrams
Package JP
I13 37
I12 38
18 PHASE1
I11 39
17 PHASE2
GND 40
16 GND
PAD
15 VREF4
14 VREF3
NC 41
Packages are not to scale VCP 42
13 VREF2
CP1 43
12 VREF1
CP2 44
11 VDD
10 PHASE3
I01 45
I02 46
I03 47
I04 48
PAD
24 I14
23 NC
22 PHASE1
21 PHASE2
20 GND
19 VREF4
18 VREF3
17 VREF2
16 VREF1
15 VDD
14 PHASE3
13 PHASE4
Terminal List Table
Number
EV JP
23
34
45
56
68
79
8 10
9 13
10 14
11 15
12 16
13 17
14 18
15 19
16 20
17 2
18 22
19 24
20 27
21 28
22 29
23 31
24 32
25 33
26 34
27 37
28 38
29 39
30 40
31 42
32 43
33 44
34 45
35 46
36 47
1 48
1, 2, 7, 11,
–
12, 23, 25,
26, 30, 35,
36, 41
––
Pin Name
OUT1A
SENSE1
OUT1B
VBB1
OUT2B
SENSE2
OUT2A
PHASE4
PHASE3
VDD
VREF1
VREF2
VREF3
VREF4
GND
PHASE2
PHASE1
I14
OUT4A
SENSE4
OUT4B
VBB2
OUT3B
SENSE3
OUT3A
I13
I12
I11
GND
VCP
CP1
CP2
I01
I02
I03
I04
Pin Description
DMOS Full-Bridge 1 Output A
Sense Resistor Terminal for Bridge 1
DMOS Full-Bridge 1 Output B
Load Supply Voltage
DMOS Full-Bridge 2 Output B
Sense Resistor Terminal for Bridge 2
DMOS Full-Bridge 2 Output A
Control Input
Control Input
Logic Supply Voltage
Analog Input
Analog Input
Analog Input
Analog Input
Ground
Control Input
Control Input
Control Input
DMOS Full-Bridge 4 Output A
Sense Resistor Terminal for Bridge 4
DMOS Full-Bridge 4 Output B
Load Supply Voltage
DMOS Full-Bridge 3 Output B
Sense Resistor Terminal for Bridge 3
DMOS Full-Bridge 3 Output A
Control Input
Control Input
Control Input
Ground
Reservoir Capacitor Terminal
Charge Pump Capacitor Terminal
Charge Pump Capacitor Terminal
Control Input
Control Input
Control Input
Control Input
NC No Connect
PAD
Exposed pad for enhanced thermal perfor-
mance. Should be soldered to the PCB.
Allegro MicroSystems, Inc.
11
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet A3988.PDF ] | |
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