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PDF CY7C1353 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1353 | |
| Descripción | 256Kx18 Flow-Through SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1353
256Kx18 Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
• Pin compatible and functionally equivalent to ZBT™
devices MCM63Z819 and MT55L256L18F
• Supports 66-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for Flow-Through operation
• Byte Write capability
• 256K x 18 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 11.0 ns (for 66-MHz device)
— 12.0 ns (for 50-MHz device)
— 14.0 ns (for 40-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100 TQFP package
• Burst Capability—linear or interleaved burst order
• Low standby power
The CY7C1353 is a 3.3V 256K by 18 Synchronous-
Flow-Through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1353 is equipped with the
advanced No Bus Latency (NoBL™) logic required to enable
consecutive Read/Write operations with data being transferred
on every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems
that require frequent Write-Read transitions.The CY7C1353 is
pin/functionally compatible to ZBT™ SRAMs MCM63Z819 and
MT55L256L18F.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted sus-
pends operation and extends the previous clock cycle. Maxi-
mum access delay from the clock rise is 9.0 ns (66-MHz de-
vice).
Write operations are controlled by the four Byte Write Select
(BWS[1:0]) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
CLK
ADV/LD
A[17:0]
CEN
CE1
CE 2
CE 3
WE
BWS [1:0]
Mode
18
CONTROL
and WRITE
LOGIC
CE
DaDta-In
Q
REG.
18
18
256KX18
18
MEMORY
18 ARRAY
DQ[15:0]
DP[1:0]
OE
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
Maximum CMOS Standby Current (mA)
Commercial
NoBL is a trademark of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
7C1353-66
11
250 mA
5 mA
7C1353-50
12.0
200 mA
5 mA
7C1353-40
14.0
175 mA
5 mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 3, 1999
1 page  
CY7C1353
dress, as described in the Single Write Access section above.
When ADV/LD is driven HIGH on the subsequent clock rise,
the chip enables (CE1, CE2, and CE3) and WE inputs are ig-
nored and the burst counter is incremented. The correct
BWS[1:0] inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Cycle Description Truth Table[1, 2, 3, 4, 5, 6]
Operation
Deselected
Address
used
External
ADV/
CE CEN LD
WE BWSx CLK
Comments
1 0 L X X L-H I/Os three-state following next rec-
ognized clock.
Suspend
- X 1 X X X L-H Clock Ignored, all operations sus-
pended.
Begin Read
External
0
0
0
1
X L-H Address Latched.
Begin Write
External
0
0
0
0 Valid L-H Address Latched, data presented
two valid clocks later.
Burst READ
Operation
Internal
X 0 1 X X L-H Burst Read Operation. Previous
access was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of Mode.
Burst WRITE
Operation
Internal
X 0 1 X Valid L-H Burst Write Operation. Previous
access was a Write operation. Ad-
dresses incremented internally in
conjunction with the state of Mode.
Bytes written are determined by
BWS[1:0].
Note:
1. X=Don't Care, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx =
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWS[1:0]. See Write Cycle Description table for details.
3. The DQ and DP pins are controlled by the current cycle and the OE signal.
4. CEN=1 inserts wait states.
5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6. OE assumed LOW.
5
5 Page 
Switching Waveforms
Burst Sequences
CY7C1353
CLK
tALS
ADV/LD
tALH
ADDRESS RA1
tCH tCL
tCYC
tAS tAH
WA2
RA3
WE
tWS tWH
BWS[1:0]
tWS tWH
tCES tCEH
CE
tCLZ
Data-
In/Out
tDOH
OQu11t a
Q1+1
Out
Device
tCDV
originally deselected
tCDV
tCHZ
tDH
Q1+2 Q1+3
Out Out
D2
In
tDS
D2+1
In
D2+2
In
tCLZ
D2+3
In
Q3
Out
Q3+1
Out
The combination of WE & BWS[1:0] defines a write cycle (see Write Cycle Description Table).
CE is the combination of CE1, CE2, and CE3. All Chip Enables need to be active in order to select
the device. Any Chip Enable can deselect the device. RAx stands for Read Address X, WAx stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS[1:0] input signals.
Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.
= DON’T CARE
= UNDEFINED
11
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet CY7C1353.PDF ] | |
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