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PDF LTC2449 Data sheet ( Hoja de datos )
| Número de pieza | LTC2449 | |
| Descripción | (LTC2444 - LTC2449) 24-Bit High Speed 8-/16-Channel ADCs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC2444/LTC2445/
LTC2448/LTC2449
24-Bit High Speed
8-/16-Channel ∆Σ ADCs with
Selectable Speed/Resolution
FEATURES
■ Up to 8 Differential or 16 Single-Ended Input
Channels
■ Up to 8kHz Output Rate
■ Up to 4kHz Multiplexing Rate
■ Selectable Speed/Resolution
■ 2µVRMS Noise at 1.76kHz Output Rate
■ 200nVRMS Noise at 13.8Hz Output Rate with
Simultaneous 50/60Hz Rejection
■ Guaranteed Modulator Stability and Lock-Up
Immunity for any Input and Reference Conditions
■ 0.0005% INL, No Missing Codes
■ Autosleep Enables 20µA Operation at 6.9Hz
■ < 5µV Offset (4.5V < VCC < 5.5V, – 40°C to 85°C)
■ Differential Input and Differential Reference with
GND to VCC Common Mode Range
■ No Latency Mode, Each Conversion is Accurate Even
After a New Channel is Selected
■ Internal Oscillator—No External Components
■ LTC2445/LTC2449 Include MUXOUT/ADCIN for
External Buffering or Gain
■ Tiny QFN 5mm xU7mm Package
APPLICATIO S
■ High Speed Multiplexing
■ Weight Scales
■ Auto Ranging 6-Digit DVMs
■ Direct Temperature Measurement
■ High Speed Data Acquisition
DESCRIPTIO
The LTC®2444/LTC2445/LTC2448/LTC2449 are 8-/16-
channel (4-/8-differential) high speed 24-bit No Latency
∆ΣTM ADCs. They use a proprietary delta-sigma architec-
ture enabling variable speed/resolution. Through a simple
4-wire serial interface, ten speed/resolution combinations
6.9Hz/280nVRMS to 3.5kHz/25µVRMS (4kHz with external
oscillator) can be selected with no latency between con-
version results or shift in DC accuracy (offset, full-scale,
linearity, drift). Additionally, a 2X speed mode can be
selected enabling output rates up to 7kHz (8kHz if an
external oscillator is used) with one cycle latency.
Any combination of single-ended or differential inputs can
be selected with a common mode input range from ground
to VCC, independent of VREF. While operating in the 1X
speed mode the first conversion following a new speed,
resolution, or channel selection is valid. Since there is no
settling time between conversions, all 8 differential chan-
nels can be scanned at a rate of 500Hz. At the conclusion
of each conversion, the converter is internally reset elimi-
nating any memory effects between successive conver-
sions and assuring stability of the high order delta-sigma
modulator.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
TYPICAL APPLICATIO
THERMOCOUPLE
Simple 24-Bit Variable Speed Data Acquisition System
4.5V TO 5.5V
CH0
CH1
•
•
•
CH7
CH8
•
•
•
CH15
COM
16-CHANNEL
MUX
REF+ VCC
FO
+
VARIABLE SPEED/
RESOLUTION
– DIFFERENTIAL
24-BIT ∆Σ ADC
SDI
SCK
SDO
CS
1µF
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
(SIMULTANEOUS 50Hz/60Hz
REJECTION AT 6.9Hz OUTPUT RATE)
4-WIRE
SPI INTERFACE
REF –
GND
LTC2448
2444 TA01
LTC2444/LTC2448
Speed vs RMS Noise
100
VCC = 5V
VVRINE+F
=
=
5V
VIN–
=
0V
2X SPEED MODE
NO LATENCY MODE
10
2.8µV AT 880Hz
280nV AT 6.9Hz
1 (50/60Hz REJECTION)
0.1
1
10 100 1000
CONVERSION RATE (Hz)
10000
2440 TA02
sn2444589 2444589fs
1
1 page  
LTC2444/LTC2445/
LTC2448/LTC2449
TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
DISCK
Internal SCK Duty Cycle
(Note 9)
● 45
55 %
fESCK
tLESCK
External SCK Frequency Range
External SCK Low Period
(Note 8)
(Note 8)
●
● 25
20 MHz
ns
tHESCK
tDOUT_ISCK
External SCK High Period
Internal SCK 32-Bit Data Output Time
(Note 8)
Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
● 25
● 41.6
35.3 30.9
● 320/fEOSC
ns
µs
s
tDOUT_ESCK
t1
t2
External SCK 32-Bit Data Output Time
CS ↓ to SDO Low Z
CS ↑ to SDO High Z
(Note 8)
(Note 12)
(Note 12)
● 32/fESCK
●0
25
●0
25
s
ns
ns
t3 CS ↓ to SCK ↓
t4 CS ↓ to SCK ↑
(Note 9)
(Notes 8, 12)
● 25
5
µs
ns
tKQMAX
tKQMIN
SCK ↓ to SDO Valid
SDO Hold After SCK ↓
(Note 5)
●
● 15
25 ns
ns
t5 SCK Set-Up Before CS ↓
t6 SCK Hold After CS ↓
● 50
●
ns
50 ns
t7 SDI Setup Before SCK ↑
t8 SDI Hold After SCK ↑
(Note 5)
(Note 5)
● 10
● 10
ns
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 4.5V to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2;
VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2.
Note 4: FO pin tied to GND or to external conversion clock source with
fEOSC = 10MHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: The converter uses the internal oscillator.
Note 8: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 9: The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output. In this mode of operation, the SCK pin
has a total equivalent load capacitance of CLOAD = 20pF.
Note 10: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in Hz.
Note 11: The converter uses the internal oscillator. FO = 0V.
Note 12: Guaranteed by design and test correlation.
Note 13: There is an internal reset that adds an additional 1µs (typ) to the
conversion time.
PI FU CTIO S
GND (Pins 1, 4, 5, 6, 31, 32, 33): Ground. Multiple
ground pins internally connected for optimum ground
current flow and VCC decoupling. Connect each one of
these pins to a common ground plane through a low
impedance connection. All 7 pins must be connected to
ground for proper operation.
BUSY (Pin 2): Conversion in Progress Indicator. This pin
is HIGH while the conversion is in progress and goes LOW
indicating the conversion is complete and data is ready. It
remains LOW during the sleep and data output states. At
the conclusion of the data output state, it goes HIGH
indicating a new conversion has begun.
EXT (Pin 3): Internal/External SCK Selection Pin. This pin
is used to select internal or external SCK for outputting/
inputting data. If EXT is tied low, the device is in the
external SCK mode and data is shifted out of the device
under the control of a user applied serial clock. If EXT is
tied high, the internal serial clock mode is selected. The
device generates its own SCK signal and outputs this on
the SCK pin. A framing signal BUSY (Pin 2) goes low
indicating data is being output.
COM (Pin 7): The common negative input (IN–) for all
single ended multiplexer configurations. The voltage on
CH0-CH15 and COM pins can have any value between
sn2444589 2444589fs
5
5 Page 
LTC2444/LTC2445/
LTC2448/LTC2449
APPLICATIO S I FOR ATIO
external SCK mode is selected by tying EXT (Pin 3) LOW
for external SCK and HIGH for internal SCK.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 37), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 36) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 36), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2444/LTC2445/LTC2448/
LTC2449 will abort any serial data transfer in progress and
start a new conversion cycle anytime a LOW-to-HIGH
transition is detected at the CS pin after the converter has
entered the data output state.
Serial Data Input (SDI)
The serial data input (SDI, Pin 34) is used to select the
speed/resolution and input channel of the LTC2444/
LTC2445/LTC2448/LTC2449. SDI is programmed by a
serial input data stream under the control of SCK during
the data output cycle, see Figure 3.
Initially, after powering up, the device performs a conver-
sion with IN+ = CH0, IN– = CH1, OSR = 256 (output rate
nominally 880Hz), and 1X speedup mode (no Latency).
Once this first conversion is complete, the device enters
the sleep state and is ready to output the conversion result
and receive the serial data input stream programming the
speed/resolution and input channel for the next conver-
sion. At the conclusion of each conversion cycle, the
device enters this state.
In order to change the speed/resolution or input channel,
the first 3 bits shifted into the device are 101. This is
compatible with the programming sequence of the
LTC2414/LTC2418. If the sequence is set to 000 or 100,
the following input data is ignored (don’t care) and the
previously selected speed/resolution and channel remain
valid for the next conversion. Combinations other than
101, 100, and 000 of the 3 control bits should be avoided.
If the first 3 bits shifted into the device are 101, then the
following 5 bits select the input channel for the following
conversion (see Tables 3 and 4). The next 5 bits select the
speed/resolution and mode 1X (no Latency) 2X (double
output rate with one conversion latency), see Table 5. If
these 5 bits are set to all 0’s, the previous speed remains
selected for the next conversion. This is useful in applica-
tions requiring a fixed output rate/resolution but need to
change the input channel. In this case, the timing and input
sequence is compatible with the LTC2414/LTC2418.
When an update operation is initiated (the first 3 bits are
101) the first 5 bits are the channel address. The first
bit, SGL, determines if the input selection is differential
(SGL = 0) or single-ended (SGL = 1). For SGL = 0, two
adjacent channels can be selected to form a differential
input. For SGL = 1, one of 8 channels (LTC2444/LTC2445)
or one of 16 channels (LTC2448/LTC2449) is selected as
the positive input. The negative input is COM for all single
ended operations. The remaining 4 bits (ODD, A2, A1, A0)
determine which channel is selected. The LTC2448/
LTC2449 use all 4 bits to select one of 16 different input
channels (see table 3) while in the case of the LTC2444/
LTC2445, A2 is always 0, and the remaining 3 bits select
one of 8 different input channels (see Table 4).
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11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC2449.PDF ] | |
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