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PDF LTC2208 Data sheet ( Hoja de datos )
| Número de pieza | LTC2208 | |
| Descripción | 16-Bit ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2208 (archivo pdf) en la parte inferior de esta página. Total 27 Páginas | ||
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Electrical Specifications Subject to Change
LTC2208
16-Bit, 130Msps ADC
FEATURES
■ Sample Rate: 130Msps
■ 78dBFS Noise Floor
■ 100dB SFDR
■ SFDR >83dB at 250MHz (1.5VP-P Input Range)
■ PGA Front End (2.25VP-P or 1.5VP-P Input Range)
■ 700MHz Full Power Bandwidth S/H
■ Optional Internal Dither
■ Optional Data Output Randomizer
■ LVDS or CMOS Outputs
■ Single 3.3V Supply
■ Power Dissipation: 1.25W
■ Clock Duty Cycle Stabilizer
■ Pin Compatible 14-Bit Version
130Msps: LTC2208 (16-Bit), LTC2208-14 (14-Bit)
■ 64-Pin QFN Package
APPLICATIOUS
■ Telecommunications
■ Receivers
■ Cellular Base Stations
■ Spectrum Analysis
■ Imaging Systems
■ ATE
DESCRIPTIO
The LTC®2208 is a 130Msps, sampling 16-bit A/D converter
designed for digitizing high frequency, wide dynamic range
signals up to input frequencies of 700MHz. The input range
of the ADC can be optimized with the PGA front end.
The LTC2208 is perfect for demanding communications
applications, with AC performance that includes 78dBFS
Noise Floor and 100dB spurious free dynamic range
(SFDR). Ultra low jitter of 70fsRMS allows undersampling
of high input frequencies with excellent noise performance.
Maximum DC specs include ±4LSB INL, ±1LSB DNL (no
missing codes) over temperature.
The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.3V.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycle.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
VCM
2.2µF
1.25V
COMMON MODE
BIAS VOLTAGE
AIN+
ANALOG
INPUT
AIN–
+
S/H
AMP
–
CLOCK/DUTY
CYCLE
CONTROL
ENC ENC
3.3V
SENSE
INTERNAL ADC
REFERENCE
GENERATOR
OVDD
16-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
OGND
VDD
GND
PGA SHDN DITH MODE LVDS RAND
ADC CONTROL INPUTS
0.5V TO 3.3V
1µF
OF
CLKOUT
D15
• CMOS
• OR
• LVDS
D0
1µF 1µF
3.3V
1µF
2208 TA01
64k Poin–t1FdFBT,,PFGINA==105.1MHz,
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10 20 30 40 50 60
FREQUENCY (MHz)
2208 G03
2208f
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LTC2208
DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
ENCODE INPUTS (ENC+, ENC–)
VID Differential Input Voltage
VICM Common Mode Input Voltage
RIN Input Resistance
CIN Input Capacitance
LOGIC INPUTS (DITH, PGA, SHDN, RAND)
VIH High Level Input Voltage
VIL Low Level Input Voltage
IIN Digital Input Current
CIN Digital Input Capacitance
LOGIC OUTPUTS (CMOS MODE)
OVDD = 3.3V
VOH
High Level Output Voltage
VOL Low Level Output Voltage
ISOURCE
Output Source Current
ISINK Output Sink Current
OVDD = 2.5V
VOH High Level Output Voltage
VOL Low Level Output Voltage
OVDD = 1.8V
VOH High Level Output Voltage
VOL Low Level Output Voltage
LOGIC OUTPUTS (LVDS MODE)
STANDARD LVDS
VOD Differential Ouptut Voltage
VOS Output Common Mode Voltage
LOW POWER LVDS
VOD Differential Ouptut Voltage
VOS Output Common Mode Voltage
CONDITIONS
Internally Set
Externally Set (Note 7)
(See Figure 2)
(Note 7)
VDD = 3.3V
VDD = 3.3V
VIN = 0V to VDD
(Note 7)
MIN TYP MAX UNITS
● 0.2
1.6
TBD
6
3
V
V
V
kΩ
pF
●2
●
●
0.8
±10
1.5
V
V
µA
pF
VDD = 3.3V
VDD = 3.3V
VOUT = 0V
VOUT = 3.3V
VDD = 3.3V
VDD = 3.3V
VDD = 3.3V
VDD = 3.3V
100Ω Differential Load
100Ω Differential Load
100Ω Differential Load
100Ω Differential Load
IO = –10µA
IO = –200µA
IO = 160µA
IO = 1.6mA
●
●
3.1
IO = –200µA
IO = 1.60mA
IO = –200µA
IO = 1.60mA
3.299
3.29
0.01
0.10
– 50
50
2.49
0.1
1.79
0.1
0.4
V
V
V
V
mA
mA
V
V
V
V
● 247
350
454
● 1.125 1.2 1.375
● 150 200
250
● 1.125 1.2 1.375
mV
V
mV
V
2208f
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TYPICAL PERFOR A CE CHARACTERISTICS
LTC2208
64K Point FFT, fIN = 70.1 MHz,
–10dB, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 10 20 30 40 50 60
FREQUENCY (MHz)
2208 G19
64K Point FFT, fIN = 70.1 MHz,
–1dB, PGA = 1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 10 20 30 40 50 60
FREQUENCY (MHz)
2208 G22
64K Point FFT, fIN1 = 67.2 MHz,
–15dBFS, fIN2 = 74.4 MHz,
–15dBFS, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 10 20 30 40 50 60
FREQUENCY (MHz)
2208 G25
64K Point FFT, fIN = 70.1 MHz,
–20dB, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 10 20 30 40 50 60
FREQUENCY (MHz)
2208 G20
SFDR (HD2 and HD3) vs
Input Frequency
105
100
95
PGA = 1
90
85 PGA = 0
80
75
70
0 50 100 150 200 250 300
INPUT FREQUENCY (MHz)
2208 G23
64K Point FFT, fIN = 140.1 MHz,
–1dB, PGA = 1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 0 10 20 30 40 50 60
FREQUENCY (MHz)
2208 G26
128K Point FFT, fIN = 70.1 MHz,
–26dB, PGA = 0, Dither “On”
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 10 20 30 40 50 60
FREQUENCY (MHz)
2208 G21
64K Point FFT, fIN1 = 67.2 MHz,
–7dBFS, fIN2 = 74.4 MHz, –7dBFS,
PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 10 20 30 40 50 60
FREQUENCY (MHz)
2208 G24
64K Point FFT, fIN = 140.1 MHz,
–1dB, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 10 20 30 40 50 60
FREQUENCY (MHz)
2208 G27
2208f
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11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet LTC2208.PDF ] | |
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