|
|
PDF LTC2206 Data sheet ( Hoja de datos )
| Número de pieza | LTC2206 | |
| Descripción | (LTC2206 / LTC2207) 16-Bit ADCs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LTC2206 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
Electrical Specifications Subject to Change
LTC2207/LTC2206
16-Bit, 105Msps/80Msps
ADCs
FEATURES
■ Sample Rate: 105Msps/80Msps
■ 78.2dBFs Noise Floor
■ 100dB SFDR
■ SFDR >83dB at 250MHz (1.5VP-P Input Range)
■ PGA Front End (2.25VP-P or 1.5VP-P Input Range)
■ 700MHz Full Power Bandwidth S/H
■ Optional Internal Dither
■ Optional Data Output Randomizer
■ Single 3.3V Supply
■ Power Dissipation: 900mW/650mW
■ Optional Clock Duty Cycle Stabilizer
■ Out-of-Range Indicator
■ Pin Compatible Family
105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit)
80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit)
■ 48-Pin QFN Package
U
APPLICATIO S
■ Telecommunications
■ Receivers
■ Cellular Base Stations
■ Spectrum Analysis
■ Imaging Systems
■ ATE
DESCRIPTIO
The LTC®2207/LTC2206 are 105Msps/80Msps, sampling
16-bit A/D converters designed for digitizing high fre-
quency, wide dynamic range signals up to input frequencies
of 700MHz. The input range of the ADC can be optimized
with the PGA front end.
The LTC2207/LTC2206 are perfect for demanding com-
munications applications, with AC performance that in-
cludes 78dB SNR and 100dB spurious free dynamic range
(SFDR). Ultralow jitter of 80fsRMS allows undersampling of
high input frequencies with excellent noise performance.
Maximum DC specs include ±4LSB INL, ±1LSB DNL (no
missing codes) over temperature.
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.3V.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycle.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
3.3V
SENSE
VCM
2.2µF
1.25V
COMMON MODE
BIAS VOLTAGE
INTERNAL ADC
REFERENCE
GENERATOR
OVDD
AIN+
ANALOG
INPUT
AIN–
+
S/H
AMP
–
16-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
CLOCK/DUTY
CYCLE
CONTROL
ENC+ ENC–
OGND
VDD
GND
PGA SHDN DITH MODE OE
ADC CONTROL INPUTS
RAND
0.5V TO 3.3V
1µF
OF
CLKOUT+
CLKOUT–
D15
•
•
•
D0
1µF 1µF
3.3V
1µF
22054 TA01
22076f
1
1 page  
www.DataSheet4U.com
LTC2207/LTC2206
DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
ENCODE INPUTS (ENC+, ENC–)
VID Differential Input Voltage
VICM Common Mode Input Voltage
RIN Input Resistance
CIN Input Capacitance
LOGIC INPUTS (DITH, PGA, SHDN, RAND)
VIH
VIL
IIN
CIN
LOGIC OUTPUTS
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
Digital Input Capacitance
OVDD = 3.3V
VOH
High Level Output Voltage
VOL Low Level Output Voltage
ISOURCE
ISINK
OVDD = 2.5V
VOH
VOL
OVDD = 1.8V
VOH
VOL
Output Source Current
Output Sink Current
High Level Output Voltage
Low Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
CONDITIONS
Internally Set
Externally Set (Note 7)
(See Figure 2)
(Note 7)
VDD = 3.3V
VDD = 3.3V
VIN = 0V to VDD
(Note 7)
MIN TYP MAX UNITS
● 0.2
1.6
1.4 3.0
6
3
V
V
kΩ
pF
●2
●
●
0.8
±10
1.5
V
V
µA
pF
VDD = 3.3V
VDD = 3.3V
VOUT = 0V
VOUT = 3.3V
VDD = 3.3V
VDD = 3.3V
VDD = 3.3V
VDD = 3.3V
IO = –10µA
IO = –200µA
IO = 160µA
IO = 1.6mA
●
●
3.1
IO = –200µA
IO = 1.60mA
IO = –200µA
IO = 1.60mA
3.299
3.29
0.01
0.10
–50
50
2.49
0.1
1.79
0.1
0.4
V
V
V
V
mA
mA
V
V
V
V
POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 9)
SYMBOL PARAMETER
VDD Analog Supply Voltage
PSHDN Shutdown Power
OVDD Output Supply Voltage
IVDD Analog Supply Current
PDIS Power Dissipation
CONDITIONS
SHDN = VDD
LTC2206
MIN TYP MAX
● 3.135 3.3 3.465
2
● 0.5
VDD
● 194 214
● 640 705
LTC2207
MIN TYP MAX
3.315 3.3 3.465
2
0.5 3.3 VDD
257 280
850 940
UNITS
V
mW
V
mA
mW
22076f
5
5 Page 
www.DataSheet4U.com
LTC2207/LTC2206
APPLICATIO S I FOR ATIO
CONVERTER OPERATION
The LTC2207/LTC2206 are CMOS pipelined multistep con-
verters with a front-end PGA. As shown in Figure 1, the con-
verter has five pipelined ADC stages; a sampled analog input
will result in a digitized value seven cycles later (see the
Timing Diagram section). The analog input is differential for
improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.
The LTC2207/LTC2206 have two phases of operation,
determined by the state of the differential ENC+/ENC– in-
put pins. For brevity, the text will refer to ENC+ greater
than ENC– as ENC high and ENC+ less than ENC– as ENC
low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplifier. In
operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages oper-
ate out of phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that ENC transitions from low to high, the voltage
on the sample capacitors is held. While ENC is high, the
held input voltage is buffered by the S/H amplifier which
drives the first pipelined ADC stage. The first stage acquires
the output of the S/H amplifier during the high phase of
ENC. When ENC goes back low, the first stage produces
its residue which is acquired by the second stage. At the
same time, the input S/H goes back to acquiring the analog
input. When ENC goes high, the second stage produces
its residue which is acquired by the third stage. An iden-
tical process is repeated for the third and fourth stages,
resulting in a fourth stage residue that is sent to the fifth
stage for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
22076f
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet LTC2206.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LTC2202 | (LTC2202 / LTC2203) 25Msps/10Msps ADCs | Linear Technology |
| LTC2203 | (LTC2202 / LTC2203) 25Msps/10Msps ADCs | Linear Technology |
| LTC2204 | (LTC2204 / LTC2205) 65Msps/40Msps | Linear Technology |
| LTC2205 | (LTC2204 / LTC2205) 65Msps/40Msps | Linear Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |