|
|
PDF CS5308 Data sheet ( Hoja de datos )
| Número de pieza | CS5308 | |
| Descripción | Two-Phase PWM Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CS5308 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
CS5308
Two−Phase PWM Controller
with Integrated Gate
Drivers for VRM 8.5
The CS5308 is a second−generation, two−phase step down
controller that incorporates all control functions required to power
next generation processors. Proprietary multi−phase architecture
guarantees balanced load current distribution and reduces overall
solution cost in high current applications. Enhanced V2™ control
architecture provides the fastest possible transient response, excellent
overall regulation, and ease of use. The CS5308 is a second generation
PWM controller because it optimizes transient response by combining
traditional Enhanced V2 with an internal PWM ramp and
fast−feedback directly from VCORE to the internal PWM comparator.
These enhancements provide greater design flexibility, facilitate use
and reduce output voltage jitter.
The multi−phase architecture reduces input and output filter ripple,
allowing for a significant reduction in filter size and inductor values
with a corresponding increase in the output inductor current slew rate.
This approach allows a considerable reduction in input and output
capacitor requirements, as well as reducing overall solution size and
cost.
The CS5308 includes VTT monitoring and timing, VTT Power
Good (VTTPGD), Power Good (PWRGD), and internal MOSFET gate
drivers to provide a “fully integrated solution” to simplify design,
minimize circuit board area, and reduce overall system cost.
Features
• Enhanced V2 Control Method
• Internal PWM Ramp
• Fast−Feedback Directly from VCORE
• 5−Bit DAC with 1% Tolerance
• Adjustable Output Voltage Positioning
• 200 kHz to 800 kHz Operation Set by Resistor
• Current Sensed through Sense Resistors or Output Inductors
• Adjustable Hiccup Mode Current Limit
• Overvoltage Protection through Synchronous MOSFETs
• Individual Current Limits for Each Phase
• On−Board Current Share Amplifiers
• 3.3 V, 1.0 mA Reference Output
• VTT Monitoring and VTT Power Good (VTTPGD)
• VCORE Power Good
• On/Off Control (through COMP Pin)
• Improved Noise Immunity
http://onsemi.com
28
1
SO−28L
DW SUFFIX
CASE 751F
MARKING
DIAGRAM
28
CS5308
AWLYYWW
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
PIN CONNECTIONS
1
COMP
VFB
VDRP
REF
ILIM
VID25
VID0
VID1
VID2
VID3
PWRGD
CSREF
CS1
CS2
28ROSC
LGND
VCCL
VCCH1
GATE(H)1
GATE(L)1
PGND
VCCL12
GATE(L)2
GATE(H)2
VCCH2
VTTPGD
VTTCT
VTT
ORDERING INFORMATION
Device
Package
Shipping
CS5308GDW28
SO−28L 27 Units/Rail
CS5308GDWR28 SO−28L 1000 Tape & Reel
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 6
1
Publication Order Number:
CS5308/D
1 page  
CS5308
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCCH1 = VCCH2 < 20 V;
4.5 V < VCCL =VCCL12 < 14 V; CGATE = 3.3 nF, RROSC = 32.4 k, CCOMP = 0.1 mF, CREF = 0.1 mF, DAC Code 01000 (1.65 V),
CVCC = 0.1 mF; unless otherwise specified.)
Characteristic
Test Conditions
Min Typ Max
Power Good Output
Power Good Fault Delay
PWRGD Low Voltage
Output Leakage Current
Lower Threshold
CSREF = DAC to DAC ± 15%
IPWRGD = 4.0 mA
VPWRGD = 5.5 V
−
25 50 100
− 250 400
− 0.1 10
−15 −12 −9.0
Upper Threshold
− 9.0 12 15
Voltage Feedback Error Amplifier
VFB Bias Current, (Note 2.)
COMP Source Current
COMP Sink Current
COMP Discharge Threshold Voltage
0.9 V < VFB < 1.9 V
COMP = 0.5 V to 2.0 V; VFB = 1.6 V
COMP = 0.5 V to 2.0 V; VFB = 1.7 V
−
9.4 10.3 11.1
15 30 60
15 30 60
0.20 0.27 0.34
Transconductance
Output Impedance
−10 mA < ICOMP < +10 mA
−
− 32 −
− 2.5 −
Open Loop DC Gain
Note 3.
60 90
−
Unity Gain Bandwidth
0.01 mF
− 400 −
PSRR @ 1.0 kHz
− − 70 −
COMP Max Voltage
COMP Min Voltage
Hiccup Latch Discharge Current
VFB = 1.6 V COMP Open
VFB = 1.7 V COMP Open
−
2.4 2.7
−
− 0.1 0.2
2.0 5.0 10
COMP Discharge Ratio
− 4.0 6.0 10
PWM Comparators
Minimum Pulse Width
Channel Startup Offset
CS1 = CS2 = CSREF
− 350 475
V(CS1) = V(CS2) = V(VFB) = V(CSREF) = 0 V;
0.3
0.4
0.5
Measure V(COMP) when GATE(H)1,2 switch
high
VTT Power Good
VTT Threshold
− 1.03 1.05 1.07
VTTPGD Low Voltage
VTTPGD Leakage Current
VTTCT Threshold Voltage
VTTCT Charge Current
VTTCT Discharge Threshold
GATES
IVTTPGD = 4.0 mA
VTTPGD = 5.5 V
Note 2.
−
−
− 0.25 0.4
− 0.1 10
1.0 1.05 1.10
15 30 45
0.24 0.32 0.38
High Voltage (AC)
Low Voltage (AC)
Measure VCCx − GATEx, Note 3.
Measure GATEx, Note 3.
− 0 1.0
− 0 0.5
Rise Time GATEx
1.0 V < GATE < 8.0 V; VCCx = 10 V
−
2. The VFB Bias Current and VTTCT Charge Currents change with the value of ROSC per Figure 4.
3. Guaranteed by design. Not tested in production.
35
80
Unit
ms
mV
mA
%
%
mA
mA
mA
V
mmho
MW
dB
kHz
dB
V
V
mA
−
ns
V
V
V
mA
V
mA
V
V
V
ns
http://onsemi.com
5
5 Page 
CS5308
APPLICATIONS INFORMATION
Overview
The CS5308 DC/DC controller from ON Semiconductor
was developed using the Enhanced V2 topology to meet
requirements of low voltage, high current loads with fast
transient requirements. Enhanced V2 combines the original
V2 topology with peak current−mode control for fast
transient response and current sensing capability. The
addition of an internal PWM ramp and implementation of
fast−feedback directly from VCORE has improved transient
response and simplified design. The CS5308 includes VTT
monitoring, VTTPGD, PWRGD, and MOSFET gate drivers
to provide a “fully integrated solution” to simplify design,
minimize circuit board area, and reduce overall system cost.
Two advantages of a multi−phase converter over a
single−phase converter are current sharing and increased
apparent output frequency. Current sharing allows the designer
to use less inductance in each phase than would be required
in a single−phase converter. The smaller inductor will
produce larger ripple currents but the total per phase power
dissipation is reduced because the RMS current is lower.
Transient response is improved because the control loop will
measure and adjust the current faster in a smaller output
inductor. Increased apparent output frequency is desirable
because the off− time and the ripple voltage of the two−phase
converter will be less than that of a single−phase converter.
Fixed Frequency Multi−Phase Control
In a multi−phase converter, multiple converters are
connected in parallel and are switched on at different times.
This reduces output current from the individual converters
and increases the apparent ripple frequency. Because several
converters are connected in parallel, output current can ramp
up or down faster than a single converter (with the same
value output inductor) and heat is spread among multiple
components.
The CS5308 controller uses two−phase, fixed frequency,
Enhanced V2 architecture to measure and control currents in
individual phases. Each phase is delayed 180° from the
previous phase. Normally, GATE(H) transitions to a high
voltage at the beginning of each oscillator cycle. Inductor
current ramps up until the combination of the current sense
signal, the internal ramp and the output voltage ripple trip
the PWM comparator and bring GATE(H) low. Once
GATE(H) goes low, it will remain low until the beginning of
the next oscillator cycle. While GATE(H) is high, the
Enhanced V2 loop will respond to line and load variations.
On the other hand, once GATE(H) is low, the loop can not
respond until the beginning of the next PWM cycle.
Therefore, constant frequency Enhanced V2 will typically
respond to disturbances within the off−time of the converter.
The Enhanced V2 architecture measures and adjusts the
output current in each phase. An additional input (CSn) for
inductor current information has been added to the V2™ loop
for each phase as shown in Figure 9. The triangular inductor
current is measured differentially across RS, amplified by
CSA and summed with the Channel Startup Offset, the
Internal Ramp, and the Output Voltage at the non−inverting
input of the PWM comparator. The purpose of the Internal
Ramp is to compensate for propagation delays in the
CS5308. This provides greater design flexibility by
allowing smaller external ramps, lower minimum pulse
widths, higher frequency operation, and PWM duty cycles
above 50% without external slope compensation. As the
sum of the inductor current and the internal ramp increase,
the voltage on the positive pin of the PWM comparator rises
and terminates the PWM cycle. If the inductor starts a cycle
with higher current, the PWM cycle will terminate earlier
providing negative feedback. The CS5308 provides a CSn
input for each phase, but the CSREF and COMP inputs are
common to all phases. Current sharing is accomplished by
referencing all phases to the same CSREF and COMP pins,
so that a phase with a larger current signal will turn off earlier
than a phase with a smaller current signal.
http://onsemi.com
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS5308.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CS5301 | Three-Phase Buck Controller with Integrated Gate Drivers and Power Good | ON Semiconductor |
| CS5301GDW32 | Three-Phase Buck Controller with Integrated Gate Drivers and Power Good | ON Semiconductor |
| CS5301GDWR32 | Three-Phase Buck Controller with Integrated Gate Drivers and Power Good | ON Semiconductor |
| CS5302 | Two-Phase Buck Controller | ON Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |