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PDF MAX9246 Data sheet ( Hoja de datos )
| Número de pieza | MAX9246 | |
| Descripción | (MAX9242 - MAX9246) 21-Bit Deserializers | |
| Fabricantes | Maxim Integrated Products | |
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19-3954; Rev 0; 1/06
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
General Description
The MAX9242/MAX9244/MAX9246 deserialize three
LVDS serial-data inputs into 21 single-ended LVCMOS/
LVTTL outputs. A separate parallel-rate LVDS clock pro-
vides the timing for deserialization. The MAX9242/
MAX9244/MAX9246 feature spread-spectrum capability,
allowing the output data and clock frequency to spread
over a specified range to reduce EMI. The single-ended
data and clock outputs are programmable for a frequency
spread of ±2%, ±4%, or no spread. The spread-spectrum
function is also available when the MAX9242/MAX9244/
MAX9246 operate in non-DC-balanced mode. The modu-
lation rate of the spread is 32kHz for a 33MHz LVDS clock
input and scales linearly with frequency. The single-
ended outputs have a separate supply, allowing +1.8V to
+5V output logic levels.
The MAX9242/MAX9244/MAX9246 feature program-
mable DC balance, allowing isolation between a serial-
izer and deserializer using AC-coupling. The MAX9242/
MAX9244/MAX9246 operate with the MAX9209/
MAX9213 serializers and are available with a rising-
edge strobe (MAX9242) or falling-edge strobe
(MAX9244/MAX9246). The LVDS inputs meet ISO
10605 ESD specifications with ±30kV Air-Gap
Discharge and ±6kV Contact Discharge ratings.
The MAX9242/MAX9244/MAX9246 are available in a
48-pin TSSOP package and operate over the -40°C to
+85°C temperature range.
Applications
Automotive Navigation Systems
Automotive DVD Entertainment Systems
Digital Copiers
Laser Printers
Selector Guide
PART
STROBE
EDGE
OVER-
SAMPLING
FREQUENCY RANGE
NON-DC
DC
BALANCE BALANCE
(MHz)
(MHz)
MAX9242 Rising Yes 20 to 40 16 to 34
MAX9244 Falling Yes 20 to 40 16 to 34
MAX9246 Falling
No
8 to 20
6 to 18
Features
♦ Programmable ±4%, ±2%, or OFF Spread-Spectrum
Output for Reduced EMI
♦ Programmable DC-Balanced or Non-DC-Balanced
Modes
♦ DC Balance Allows AC-Coupling for Wider Input
Common-Mode Voltage Range
♦ Spread Spectrum Operates in DC-Balanced or
Non-DC-Balanced Mode
♦ π / 4 Deskew by Oversampling (MAX9242/MAX9244)
♦ 16MHz-to-34MHz (DC-Balanced) and 20MHz-to-
40MHz (Non-DC-Balanced) Operation
(MAX9242/MAX9244)
♦ 6MHz-to-18MHz (DC-Balanced) and 8MHz-to-20MHz
(Non-DC-Balanced) Operation (MAX9246)
♦ Rising-Edge (MAX9242) or Falling-Edge
(MAX9244/MAX9246) Output Strobe
♦ High-Impedance Outputs when PWRDWN is Low
Allow Output Busing
♦ Fail-Safe Inputs in Non-DC-Balanced Mode
♦ Separate Output Supply Allows Interface to +1.8V,
+2.5V, +3.3V, and +5V Logic
♦ LVDS Inputs Meet ISO 10605 ESD Protection at
±30kV Air-Gap Discharge and ±6kV Contact
Discharge
♦ LVDS Inputs Meet IEC 61000-4-2 Level 4 ESD
Protection at ±15kV Air-Gap Discharge and ±8kV
Contact Discharge
♦ LVDS Inputs Conform to ANSI TIA/EIA-644 Standard
♦ +3.3V Main Power Supply
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
PKG
CODE
MAX9242EUM -40°C to +85°C 48 TSSOP
U48-1
MAX9244EUM -40°C to +85°C 48 TSSOP
U48-1
MAX9246EUM -40°C to +85°C 48 TSSOP
U48-1
Devices are available in lead-free packaging. Specify lead free by
adding a + symbol at the end of the part number when ordering.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = LVDSVCC = PLLVCC = +3.0V to +3.6V, VCCO = +3.0V to +3.6V, CL = 8pF, PWRDWN = high; SSG = high, open, or low;
DCB = high or low, differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID / 2| to 2.4V - |VID / 2|, unless
otherwise noted. Typical values are at VCC = VCCO = LVDSVCC = PLLVCC = +3.3V, |VID| = 0.2V, VCM = +1.25V, TA = +25°C.) (Notes 6, 7, 8)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Deserializer Phase-Locked-
Loop Set
RPLLS Figure 7
65,600 x
RCIP
ns
Deserializer Power-Down Delay RPDD Figure 8
100 ns
Deserializer Phase-Locked-
Loop Set from SSG Change
RPLLS2 Figure 9
32,800 x
RCIP
ns
Spread-Spectrum Output
Frequency
SSG = high,
Figure 10
fRxCLKOUT
SSG = open,
Figure 10
Maximum output
frequency
Minimum output
frequency
Maximum output
frequency
Minimum output
frequency
fRxCLKIN
+ 3.6%
fRxCLKIN
- 4.4%
fRxCLKIN
+ 1.8%
fRxCLKIN
- 2.2%
fRxCLKIN
+ 4.0%
fRxCLKIN
- 4.0%
fRxCLKIN
+ 2.0%
fRxCLKIN
- 2.0%
fRxCLKIN
+ 4.4%
fRxCLKIN
- 3.6%
fRxCLKIN
+ 2.2%
fRxCLKIN
- 1.8%
MHz
Spread-Spectrum Modulation
Frequency
fSSM
SSG = low
Figure 10
fRxCLKIN
fRxCLKIN
fRxCLKIN /
1016
Hz
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground,
except VTH and VTL.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA = +25°C.
Note 3: To provide a mid level, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
must be less than ±10µA.
Note 4: RxCLKOUT limits are scaled based on RxOUT_ measurements, design, and characterization data.
Note 5: One output shorted at a time. Current out of the pin.
Note 6: VTH, VTL, and AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set
at ±6 sigma.
Note 7: CL includes probe and test jig capacitance.
Note 8: RCIP is the period of RxCLKIN. RCOP is the period of RxCLKOUT.
Note 9: RSKM is measured with less than 150ps cycle-to-cycle jitter on RxCLKIN.
_______________________________________________________________________________________ 5
5 Page 
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
Pin Description
PIN NAME
FUNCTION
1 RxOUT17
Channel 2 Single-Ended Outputs
2 RxOUT18
3, 25, 32,
38, 44
GND Ground
4 RxOUT19
Channel 2 Single-Ended Outputs
5 RxOUT20
6
SSG
Three-Level-Logic, Spread-Spectrum Generator Control Input. SSG selects the frequency spread of
RxCLKOUT relative to RxCLKIN (see Table 3).
Three-Level-Logic, DC-Balance Control Input. DCB selects DC-balanced, non-DC-balanced, or reserved
7
DCB
operation (see Table 1).
8 RxIN0- Inverting Channel 0 LVDS Serial-Data Input
9 RxIN0+ Noninverting Channel 0 LVDS Serial-Data Input
10 RxIN1- Inverting Channel 1 LVDS Serial-Data Input
11 RxIN1+ Noninverting Channel 1 LVDS Serial-Data Input
12
LVDSVCC
LVDS Supply Voltage. Bypass LVDSVCC to GND with 0.1µF and 0.001µF capacitors in parallel as close to
the pin as possible.
13, 18 LVDSGND LVDS Ground
14 RxIN2- Inverting Channel 2 LVDS Serial-Data Input
15 RxIN2+ Noninverting Channel 2 LVDS Serial-Data Input
16 RxCLKIN- Inverting LVDS Parallel-Rate Clock Input
17 RxCLKIN+ Noninverting LVDS Parallel-Rate Clock Input
19, 21 PLLGND PLL Ground
20
PLLVCC
PLL Supply Voltage. Bypass PLLVCC to GND with 0.1µF and 0.001µF capacitors in parallel as close to
the pin as possible.
22
PWRDWN
5V-Tolerant LVTTL/LVCMOS Power-Down Input. PWRDWN is internally pulled down to GND. Outputs are
high impedance when PWRDWN = low or open.
23
RxCLKOUT
Parallel-Rate Clock Single-Ended Output. The MAX9242 has a rising-edge strobe. The MAX9244/MAX9246
have a falling-edge strobe.
24 RxOUT0
26 RxOUT1 Channel 0 Single-Ended Outputs
27 RxOUT2
28, 36, 48
VCCO
Output Supply Voltage. Bypass each VCCO to GND with 0.1µF and 0.001µF capacitors in parallel as
close to the pin as possible.
29 RxOUT3
30 RxOUT4
Channel 0 Single-Ended Outputs
31 RxOUT5
33 RxOUT6
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet MAX9246.PDF ] | |
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