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PDF ST72324J Data sheet ( Hoja de datos )

Número de pieza ST72324J
Descripción 8-BIT MCU
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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ST72324J/K
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,
4 TIMERS, SPI, SCI INTERFACE
PRELIMINARY DATA
s Memories
– 8 to 32K dual voltage High Density Flash (HD-
Flash) or ROM with read-out protection capa-
bility. In-Application Programming and In-
Circuit Programming for HDFlash devices
– 384 to 1K bytes RAM
– HDFlash endurance: 100 cycles, data reten-
tion: 20 years at 55°C
s Clock, Reset And Supply Management
TQFP44
10 x 10
TQFP32
7x7
– Enhanced low voltage supervisor (LVD) for
main supply with 3 programmable reset
thresholds and auxiliary voltage detector
(AVD) with interrupt capability
– Clock sources: crystal/ceramic resonator os-
cillators, internal or external RC oscillator,
clock security system and bypass for external
clock
– PLL for 2x frequency multiplication
– Four Power Saving Modes: Halt, Active-Halt,
Wait and Slow
s Interrupt Management
– Nested interrupt controller
– 10 interrupt vectors plus TRAP and RESET
– 9/6 external interrupt lines (on 4 vectors)
s Up to 32 I/O Ports
SDIP42
600 mil
SDIP32
400 mil
s 2 Communication Interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface (LIN com-
patible)
s 1 Analog Peripheral
– 10-bit ADC with up to 12 input pins
– 32/24 multifunctional bidirectional I/O lines
– 22/17 alternate function lines
– 12/10 high sink outputs
s 4 Timers
– Main Clock Controller with: Real time base,
Beep and Clock-out capabilities
– Configurable watchdog timer
– 16-bit Timer A with: 1 input capture, 1 output
compare, external clock input, fixed freq.
PWM and pulse generator modes
– 16-bit Timer B with: 2 input captures, 2 output
compares, variable freq. PWM and pulse gen-
erator modes
s Instruction Set
– 8-bit Data Manipulation
– 63 Basic Instructions
– 17 main Addressing Modes
– 8 x 8 Unsigned Multiply Instruction
s Development Tools
– Full hardware/software development package
– In-Circuit Testing capability
Device Summary
Features
ST72(F)324(J/K)6
ST72(F)324(J/K)4
ST72(F)324(J/K)2
Program memory - bytes
RAM (stack) - bytes
Operating Voltage
Temp. Range (ROM)
Temp. Range (Flash)
Packages
32K 16K
8K
1024 (256)
512 (256)
384 (256)
3.8V to 5.5V (low voltage version planned with 3.0 to 3.6V range)
up to -40°C to +125°C
up to -40°C to +125°C
-40°C to +85 °C
SDIP42 (JxB), TQFP44 10x10 (JxT),SDIP32 (KxB), TQFP32 7x7 (KxT)
Rev. 1.6
October 2002
1/156
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change witho1ut notice.

1 page




ST72324J pdf
Table of Contents
12.4.4 WAIT and SLOW WAIT Modes (ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.4.5 HALT and ACTIVE-HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.4.6 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.4.7 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
12.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
12.5.5 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
12.5.6 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.7.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.7.3 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
12.7.4 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.10.116-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 139
12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
12.12.1ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
13.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
14 ST72324J/K DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . 148
14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 150
14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
14.3.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
14.5 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
15 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
156
5/156
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ST72324J arduino
ST72324J/K
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD
are not implemented). See See “I/O PORTS” on page 44. and Section 12.8 I/O PORT PIN CHARACTER-
ISTICS for more details.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, an RC oscillator, or an external source to
the on-chip oscillator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARAC-
TERISTICS for more details.
4. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up con-
figuration after reset. The configuration of these pads must be kept at reset state to avoid added current
consumption.
11/156

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