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PDF 56F805 Data sheet ( Hoja de datos )
| Número de pieza | 56F805 | |
| Descripción | 16-bit Hybrid Controller | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Freescale Semiconductor, Inc.
DSP56F805/D
Rev. 12.0, 02/2004
56F805
Technical Data
56F805 16-bit Hybrid Controller
• Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
• 31.5K × 16-bit words Program Flash
• 512 × 16-bit words Program RAM
• 4K × 16-bit words Data Flash
• 2K × 16-bit words Data RAM
• 2K × 16-bit words Boot Flash
• Up to 64K × 16-bit words each of external
Program and Data memory
• Two 6-channel PWM Modules
• Two 4-channel, 12-bit ADCs
• Two Quadrature Decoders
• CAN 2.0 B Module
• Two Serial Communication Interfaces (SCIs)
• Serial Peripheral Interface (SPI)
• Up to four General Purpose Quad Timers
• JTAG/OnCETM port for debugging
• 14 Dedicated and 18 Shared GPIO lines
• 144-pin LQFP Package
6
PWM Outputs
Current Sense Inputs
3
Fault Inputs
4
6
PWM Outputs
Current Sense Inputs
3
Fault Inputs
4
A/D1
4 A/D2 ADC
4 VREF
Quadrature
Decoder 0/
4 Quad Timer A
PWMA
PWMB
RSTO
EXTBOOT
RESET IRQB
IRQA
6
JTAG/
OnCE
Port
VPP VCAPC VDD
28
VSS
8*
VDDA
VSSA
Digital Reg Analog Reg
Low Voltage
Supervisor
Interrupt
Controller
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Quadrature
Decoder 1/
Program Memory
4
Quad B Timer
32252 x 16 Flash
512 x 16 SRAM
Quad Timer C
••
PAB
PDB
•
16-Bit
PLL
CLKO
2 Boot Flash
Quad Timer D
2048 x 16 Flash
4 / Alt Func
CAN 2.0A/B
Data Memory
2
SCI0
4096 x 16 Flash
2048 x 16 SRAM
or
2 GPIO
56800
XDB2
Core
CGDB
• • •XAB1
•XAB2
•INTERRUPT
IPBB
Clock Gen
XTAL
EXTAL
SCI1
or
COP/
CONTROLS CONTROLS
16 16
External 6
Address Bus
A[00:05]
A[06:15] or
2 GPIO
Watchdog
COP RESET
SPI
Application-
MODULE CONTROLS
or Specific
4
GPIO
Memory &
Dedicated
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
External
Bus
Interface
Unit
Switch
External
Data Bus
Switch
Bus
GPIO-E2:E3 &
10 GPIO-A0:A7
D[00:15]
16
PS Select
DS Select
GPIO
Peripherals
Control
WR Enable
14 RD Enable
*includes TCS pin which is reserved for factory use and is tied to VSS
Figure 1. 56F805 Block Diagram
© Motorola, Inc., 2004. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com
1 page  
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Freescale Semiconductor, Inc.
Product Documentation
1.4 Product Documentation
The four documents listed in Table 2 are required for a complete description and proper design with the
56F805. Documentation is available from local Motorola distributors, Motorola semiconductor sales
offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors.
Table 1. 56F805 Chip Documentation
Topic
Description
Order Number
DSP56800
Family Manual
DSP56F801/803/805/
807 User’s Manual
56F805
Technical Data Sheet
56F805
Product Brief
56F805
Errata
Detailed description of the 56800 family architecture, and
16-bit core processor and the instruction set
DSP56800FM/D
Detailed description of memory, peripherals, and interfaces DSP56F801-7UM/D
of the 56F801, 56F803, 56F805, and 56F807
Electrical and timing specifications, pin descriptions, and
package descriptions (this document)
DSP56F805/D
Summary description and block diagram of the 56F805
core, memory, peripherals and interfaces
DSP56F805PB/D
Details any chip issues that might be present
DSP56F805E/D
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Examples:
Signal/Symbol
Logic State
Signal State
Voltage1
PIN
True
Asserted
VIL/VOL
PIN
False
Deasserted
VIH/VOH
PIN
True
Asserted
VIH/VOH
PIN
False
Deasserted
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
VIL/VOL
56F805 Technical Data
For More Information On This Product,
Go to: www.freescale.com
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Freescale Semiconductor, Inc.
GPIO Signals
Table 10. Interrupt and Program Control Signals (Continued)
No. of
Pins
Signal
Name
Signal
Type
State
During
Reset
Signal Description
1
RSTO
Output Output Reset Output—This output reflects the internal reset state of the
chip.
1
EXTBOOT
Input
Input External Boot—This input is tied to VDD to force device to boot
(Schmitt)
from off-chip memory. Otherwise, it is tied to VSS.
2.6 GPIO Signals
Table 11. Dedicated General Purpose Input/Output (GPIO) Signals
No. of
Pins
Signal
Name
Signal State During
Type
Reset
Signal Description
8 GPIOB0– Input
GPIOB7
or
Output
6 GPIOD0– Input
GPIOD5
or
Output
Input
Input
Port B GPIO—These eight dedicated General Purpose I/O
(GPIO) pins can be individually programmed as input or output
pins.
After reset, the default state is GPIO input.
Port D GPIO—These six dedicated General Purpose I/O (GPIO)
pins can be individually programmed as input or output pins.
After reset, the default state is GPIO input.
2.7 Pulse Width Modulator (PWM) Signals
Table 12. Pulse Width Modulator (PWMA and PWMB) Signals
No. of
Pins
Signal Name
Signal
Type
State During
Reset
Signal Description
6
PWMA0–5
Output
Tri- stated PWMA0–5—These are six PWMA output pins.
3 ISA0–2 Input
Input
ISA0–2—These three input current status pins are used for
(Schmitt)
top/bottom pulse width correction in complementary
channel operation for PWMA.
4 FAULTA0–3 Input
(Schmitt)
Input
FAULTA0–3—These four Fault input pins are used for
disabling selected PWMA outputs in cases where fault
conditions originate off-chip.
6 PWMB0–5 Output
Output
PWMB0–5—These are six PWMB output pins.
3 ISB0–2 Input
Input
ISB0–2— These three input current status pins are used
(Schmitt)
for top/bottom pulse width correction in complementary
channel operation for PWMB.
4 FAULTB0–3 Input
(Schmitt)
Input
FAULTB0–3—These four Fault input pins are used for
disabling selected PWMB outputs in cases where fault
conditions originate off-chip.
56F805 Technical Data
For More Information On This Product,
Go to: www.freescale.com
11
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| Páginas | Total 48 Páginas | |
| PDF Descargar | [ Datasheet 56F805.PDF ] | |
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