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PDF MC74LVX245 Data sheet ( Hoja de datos )
| Número de pieza | MC74LVX245 | |
| Descripción | LOW-VOLTAGE CMOS | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal Bus Transceiver
With 5V-Tolerant Inputs
The MC74LVX245 is an advanced high speed CMOS octal bus
transceiver.
It is intended for two–way asynchronous communication between data
buses. The direction of data transmission is determined by the level of the
T/R input. The output enable pin (OE) can be used to disable the device,
so that the buses are effectively isolated.
All inputs are equipped with protection circuits against static discharge.
• High Speed: tPD = 4.7ns (Typ) at VCC = 3.3V
• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Low Noise: VOLP = 0.8V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
APPLICATION NOTES
1. Do not force a signal on an I/O pin when it is an active output, damage may
occur.
2. All floating (high impedence) input or I/O pins must be fixed by means of
pull up or pull down resistors or bus terminator ICs.
3. A parasitic diode is formed between the bus and VCC terminals. Therefore,
the LVX245 cannot be used to interface 5V to 3V systems directly.
VCC OE B0 B1 B2 B3 B4 B5 B6 B7
20 19 18 17 16 15 14 13 12 11
MC74LVX245
LVX
LOW–VOLTAGE CMOS
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
1 2 3 4 5 6 7 8 9 10
T/R A0 A1 A2 A3 A4 A5 A6 A7 GND
Figure 1. 20–Lead Pinout (Top View)
PIN NAMES
Pins
Function
OE
T/R
A0–A7
B0–B7
Output Enable Input
Transmit/Receive Input
Side A 3–State Inputs or 3–State
Outputs
Side B 3–State Inputs or 3–State
Outputs
6/97
© Motorola, Inc. 1997
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MC74LVX245
Input
A or B
50%
tPLH
Output
B or A
50% VCC
Figure 3.
SWITCHING WAVEFORMS
T/R
VCC
GND
tPHL
OE
A or B
A or B
50% VCC
tPZL
tPLZ
50% VCC
tPZH tPHZ
50% VCC
Figure 4.
50%
50% VCC
VCC
GND
VCC
GND
HIGH
IMPEDANCE
VOL +0.3V
VOH –0.3V
HIGH
IMPEDANCE
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
* Includes all probe and jig capacitance
Figure 5. Propagation Delay Test Circuit
* Includes all probe and jig capacitance
Figure 6. Three–State Test Circuit
LCX DATA
DataSheetB4RU13.c39om— REV 3
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MOTOROLA
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| PDF Descargar | [ Datasheet MC74LVX245.PDF ] | |
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