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PDF HY62256B Data sheet ( Hoja de datos )
| Número de pieza | HY62256B | |
| Descripción | 32K x 8-Bit CMOS SRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY62256B Series
32Kx8bit CMOS SRAM
DESCRIPTION
The HY62256B is a high-speed, low power and
32,786 X 8-bits CMOS Static Random Access
Memory fabricated using Hyundai's high
performance CMOS process technology. It is
suitable for use in low voltage operation and
battery back-up application. This device has a
data retention mode that guarantees data to
remain valid at the minimum power supply
voltage of 2.0 volt.
FEATURES
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Low power consumption
• Battery backup(L/LL-part)
- 2.0V(min.) data retention
• Standard pin configuration
- 28 pin 600 mil PDIP
- 28 pin 330mil SOP
- 28 pin 8x13.4 mm TSOP-I
(Standard and Reversed)
Product Voltage Speed
No. (V) (ns)
HY62256B
5.0 55/70/85
Note 1. Current value is max.
Operation
Current(mA)
8
Standby Current(uA)
L LL
1mA 100
25
Temperature
(°C)
0~70(Normal)
PIN CONNECTION
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
Vcc
/WE
A13
A8
A9
A11
/OE
A14
A12
A7
A6
A5
A4
A3
21 A10 A2
1
2
3
4
5
6
7
8
20 /CS A1 9
19
18
17
16
15
I/O8 A0
I/O7 I/O1
I/O6
I/O5
I/O4
I/O2
I/O3
Vss
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PDIP
SOP
Vcc
/WE
A13
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
/OE
A11
A9
A8
A13
/WE
Vcc
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 A10
27 /CS
26 I/O8
25 I/O7
24 I/O6
23 I/O5
22 I/O4
21 Vss
20 I/O3
19 I/O2
18 I/O1
17 A0
16 A1
15 A2
TSOP-I(Standard)
A3
A4
A5
A6
A7
A12
A14
Vcc
/WE
A13
A8
A9
A11
/OE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15 A2
16 A1
17 A0
18 I/O1
19 I/O2
20 I/O3
21 Vss
22 I/O4
23 I/O5
24 I/O6
25 I/O7
26 I/O8
27 /CS
28 A10
TSOP-I(Reversed)
PIN DESCRIPTION
Pin Name
/CS
/WE
/OE
A0 ~ A14
I/O1 ~ I/O8
Vcc
Vss
Pin Function
Chip Select
Write Enable
Output Enable
Address Inputs
Data Input/Output
Power(+5.0V)
Ground
BLOCK DIAGRAM
A0 ROW DECODER
A14
/CS
/OE
/WE
MEMORY ARRAY
512x512
I/O1
I/O8
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.04 /Jan.99
Hyundai Semiconductor
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HY62256B Series
Note(READ CYCLE):
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and arenot
referenced to output voltage levels.
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device
and from device to device.
3. /WE is high for the read cycle.
READ CYCLE 2
ADDR
Data
Out
tAA
tOH
Previous Data
tRC
Data Valid
tOH
Note(READ CYCLE):
1. /WE is high for the read cycle.
2. Device is continuously selected /CS= VIL.
3. /OE =VIL.
WRITE CYCLE 1(/OE Clocked)
ADDR
tWC
OE
CS
WE
Data In
Data
Out
tAS
tOHZ
tAW
tCW
tWP tWR
tDW
tDH
Data Valid
Rev.04 /Jan.99
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HY62256B.PDF ] | |
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