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PDF ICS9FG108 Data sheet ( Hoja de datos )
| Número de pieza | ICS9FG108 | |
| Descripción | Programmable FTG for Differential P4 CPU | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9FG108
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
Recommended Application:
Pin Configuration
Frequency Timing Generator for Differential CPU, PCI-
Express & SATA clocks
XIN/CLKIN 1
X2 2
Features:
• Generates common frequencies from 14.318 MHz or
25 MHz
• Crystal or reference input
VDD
GND
REFOUT
FS2
OE_7**
3
4
5
6
7
• 8 - 0.7V current-mode differential output pairs
• Supports Serial-ATA at 100 MHz
• Two spread spectrum modes: 0 to -0.5 downspread
and +/-0.25% centerspread
• Unused inputs may be disabled in either driven or Hi-
Z state for power management.
• Programmable OE Polarity
DIF_7 8
DIF_7# 9
VDD 10
DIF_6 11
DIF_6# 12
OE_6* 13
VDD 14
GND 15
• M/N Programming
OE_5* 16
DIF_5 17
Key Specifications:
• Output cycle-to-cycle jitter < 50 ps
DIF_5# 18
VDD 19
DIF_4 20
• Output to output skew < 65 ps
• +/-300 ppm frequency accuracy on output clocks
• +/-150 ppm frequency accuracy @100 MHz outputs
DIF_4# 21
OE_4** 22
SDATA 23
SCLK 24
48 VDDA
47 GNDA
46 IREF
45 FS0
44 FS1
43 OE_0**
42 DIF_0
41 DIF_0#
40 VDD
39 DIF_1
38 DIF_1#
37 OE_1*
36 VDD
35 GND
34 OE_2*
33 DIF_2
32 DIF_2#
31 VDD
30 DIF_3
29 DIF_3#
28 OE_3**
27 SEL14M_25M#
26 SPREAD
25 DIF_STOP#
Frequency Select Table
SEL14M_25M#
(FS3)
FS2 FS1 FS0 OUTPUT(MHz)
0
000
100.00
0
001
125.00
0
010
133.33
0
011
166.67
0
100
200.00
0
101
266.66
0
110
333.33
0
111
400.00
1
000
100.00
1
001
125.00
1
010
133.33
1
011
166.67
1
100
200.00
1
101
266.66
1
110
333.33
1
111
400.00
Note:
Pin names followed by '**' have 120 Kohm pull DOWN resistors
Pin names followed by '*' have 120 Kohm pull UP resistors
48-pin SSOP & TSSOP
0823E—04/13/06
1 page  
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS9FG108
Absolute Max
Symbol
Parameter
VDD_A
3.3V Core Supply Voltage
VDD_In 3.3V Logic Input Supply Voltage
Ts
Tambient
Tcase
ESD prot
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
GND - 0.5
-65
0
2000
Max
VDD + 0.5V
VDD + 0.5V
150
70
115
Units
V
V
°C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP
Operating Supply Current
Input Frequency3
Pin Inductance1
Input/Output
Capacitance1
IDD3.3STOP
Fi
Lpin
CIN
COUT
Clk Stabilization1,2
TSTAB
Modulation Frequency
DIF output enable
fMOD
tDIFOE
3.3 V +/-5%
3.3 V +/-5%
VIN = VDD
VIN = 0 V; Inputs with no pull-
up resistors
VIN = 0 V; Inputs with pull-up
resistors
Full Active, CL = Full load;
f = 400 MHz
Full Active, CL = Full load;
f = 100 MHz
All outputs stopped driven
All outputs stopped Hi-Z
VDD = 3.3 V
Logic Inputs
Output pin capacitance
From VDD Power-Up and after
input clock stabilization to 1st
clock
Triangular Modulation
DIF output enable after
DIF_Stop# de-assertion
2
VSS -
0.3
-5
-5
-200
14
1.5
30
VDD + 0.3 V
0.8 V
5 uA
uA
uA
215 250 mA
180 200 mA
180 200
51 60
mA
mA
25 MHz
7 nH
5 pF
6 pF
1 1.8 ms
33 kHz
9.8 15 ns
1
1
1
1
3
1
1
1
1,2
1
1
Input Rise and Fall times tR/tF
20% to 80% of VDD
5 ns
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25
MHz to meet
1
0823E—04/13/06
5
5 Page 
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS9FG108
SMBus Table: Byte Count Register
Byte 6
Pin #
Name
Bit 7
-
BC7
Bit 6
-
BC6
Bit 5
-
BC5
Bit 4
-
BC4
Bit 3
-
BC3
Bit 2
-
BC2
Bit 1
-
BC1
Bit 0
-
BC0
Control Function
Writing to this register
will configure how many
bytes will be read back,
default is 07 = 7 bytes.
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBus Table: Reserved Register
Byte 7
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Type
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Table: Reserved Register
Byte 8
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Type
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Table: M/N Programming Enable
Byte 9
Pin #
Name
Control Function
Type
Bit 7
Bit 6
Bit 5
-
-
5
M/N_EN
OE_Polarity
REFOUT_En
PLL M/N Programming
Enable
Select Polarity of OE
inputs
Enables/Disables REF
RW
RW
RW
Bit 4
Reserved
Bit 3
Reserved
Bit 2
Reserved
Bit 1
Reserved
Bit 0
Reserved
0
-
-
-
-
-
-
-
-
0
0
0
Disable
OE#
Disable
1 PWD
-0
-0
-0
-0
-0
-1
-1
-1
1 PWD
X
X
X
X
X
X
X
X
1 PWD
X
X
X
X
X
X
X
X
1
Enable
OE
Enable
PWD
0
1
1
0
0
0
0
0
0823E—04/13/06
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ICS9FG108.PDF ] | |
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