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PDF LM5032 Data sheet ( Hoja de datos )
| Número de pieza | LM5032 | |
| Descripción | High Voltage Dual Interleaved Current Mode Controller | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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www.DataSheet4U.com
March 2005
LM5032
High Voltage Dual Interleaved Current Mode Controller
General Description
The LM5032 dual current mode PWM controller contains all
the features needed to control either two independent for-
ward dc/dc converters or a single high current converter
comprised of two interleaved power stages. The two control-
ler channels operate 180˚ out of phase thereby reducing
input ripple current. The LM5032 includes a startup regulator
that operates over a wide input range up to 100V and
compound (bipolar + CMOS) gate drivers that provide a
robust 2.5A peak sink current. The adjustable maximum
PWM duty cycle reduce stress on the primary side MOSFET
switches. Additional features include programmable line
under-voltage lockout, cycle-by-cycle current limit, hiccup
mode fault operation with adjustable response time, PWM
slope compensation, soft-start, and a 2 MHz capable oscil-
lator with synchronization capability.
Features
n Two independent PWM current mode controllers
n Integrated high voltage startup regulator
n Compound 2.5A main output gate drivers
n Single resistor oscillator setting to 2 MHz
n Synchronizable oscillator
n Programmable maximum duty cycle
n Maximum duty cycle fold-back at high line voltage
n Adjustable timer for hiccup mode current limiting
n Integrated slope compensation
n Adjustable line under-voltage lockout
n Independently adjustable soft-start (each regulator)
n Direct interface with opto-coupler transistor
n Thermal shutdown
Applications
n Telecommunication Power Converters
n Industrial Power Converters
n +42V Automotive Systems
Packages
n TSSOP-16
Typical Application Circuit
Dual Interleaved Regulators with Independent Outputs
20135001
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© 2005 National Semiconductor Corporation DS201350
www.national.com
1 page  
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN to GND
VCC to GND
RT/SYNC, RES and DCL to GND
CS Pins to GND
All other inputs to GND
ESD Rating (Note 5)
Human Body Model
-0.3V to 105V
-0.3V to 16V
-0.3V to 5.5V
-0.3V to 1.25V
-0.3V to 7V
2kV
Storage Temperature Range
Junction Temperature
Lead Temperature (Soldering 4 sec),
(Note 2)
-55˚C to 150˚C
150˚C
260˚C
Operating Ratings (Note 1)
VIN Voltage
External Voltage Applied to VCC
Operating Junction Temperature
13.0V to 100V
8V to 15V
-40˚C to +125˚C
Electrical Characteristics
Specifications with standard typeface are for TJ = 25˚C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V externally applied, RT = RDCL = 42.2kΩ, UVLO = 1.5V, unless otherwise
stated (Note 3) and (Note 4).
Symbol
Parameter
Conditions
Min Typ Max Units
Startup Regulator (VIN, VCC Pins)
VCCReg
ICC(Lim)
VCC UVT
IIN
ICCIn
VCC voltage
Ext. supply disconnected.
VCC current limit
VCC = 0V.
VCC Under-voltage threshold Ext. supply disconnected, VIN =11V.
(VCC increasing)
VCC decreasing
Startup regulator current
VIN = 90V, UVLO = 0V
Supply current into VCC
from external source
Output loads = open, VCC = 10V
7.4
19
VCC -
300 mV
5.5
7.7
22
VCC -
100 mV
6.2
500
4.3
8
6.9
600
7
V
mA
V
V
µA
mA
UVLO
UVLO
Under-voltage threshold
1.22
1.25 1.28 V
IHYST
Hysteresis current
Current Sense Input (CS1, CS2 Pins)
16 20 24 µA
CS Current Limit Threshold
0.45
0.5 0.55 V
CS delay to output
CS1 (CS2) taken from zero to 1.0V.
Time for OUT1 (OUT2) to fall to 90% of
VCC. Output load = 0 pF.
40 ns
Leading edge blanking time
at CS1 (CS2)
50 ns
CS1 (CS2) sink impedance Internal pull-down FET on.
(clocked)
30 55 Ω
RCS Equivalent input resistance CS taken from 0.2V to 0.5V, internal
at CS
FET off.
42 kΩ
Current Limit Restart (RES Pin)
ResTh
Threshold
2.4
2.55 2.7
V
Charge source current
15 20 25 µA
Discharge sink current
7.5 10 12.5 µA
Soft-start (SS1, SS2 Pins)
ISS Current source (normal
operation)
35 50 65 µA
Current source during a
current limit restart
0.7 1 1.3 µA
VSS Open circuit voltage
5V
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Functional Description
The LM5032 contains all the features necessary to imple-
ment two independently regulated current mode dc/dc con-
verters, or a single high current converter comprised of two
parallel interleaved channels using the Forward converter
topology. The two controllers operate 180˚ out of phase from
a common oscillator, thereby reducing input ripple current.
Each regulator channel contains a complete PWM controller,
current sense input, soft-start circuit, and gate driver output.
Common to both channels are the startup and VCC regulator,
line under-voltage lockout, 2 MHz capable oscillator, maxi-
mum duty cycle control, and the hiccup mode fault protection
circuit.
The gate driver outputs (OUT1, OUT2) are designed to drive
N-channel MOSFETs. Their compound configuration re-
duces the turn-off-time, thereby reducing switching losses.
Additional features include thermal shutdown, slope com-
pensation, and the oscillator synchronization capability.
Line Under-Voltage Lock Out,
UVLO, Shutdown
The LM5032 contains a line under-voltage lockout circuit
(UVLO) designed to enable the VCC regulator and output
drivers when the system voltage (VPWR) exceeds the de-
sired level (see Figure 15). VPWR is the voltage normally
applied to the transformer primary, and usually connected to
the VIN pin (see the schematic on Page 1). The threshold at
the UVLO comparator is 1.25V. An external resistor divider
connected from VPWR to ground provides 1.25V at the UVLO
pin when VPWR is increased to the desired turn-on threshold.
When VPWR is below the threshold the VCC regulator and
output drivers are disabled, and the internal 20 µA current
source is off. When VPWR reaches the threshold, the com-
parator output switches low to enable the internal circuits
and the 20 µA current source. The 20 µA flows into the
external divider’s junction, raising the voltage at UVLO,
thereby providing hysteresis. Internally the voltage at UVLO
also drives the Maximum Duty Cycle Limiter circuit (de-
scribed below), which may influence the values chosen for
the UVLO pin resistors. At maximum VPWR, the voltage at
UVLO should not exceed 6V. Refer to the Applications Infor-
mation section for a procedure to calculate the resistors
values.
The LM5032 controller can be shutdown by forcing the
UVLO pin below 1.25V with an external switch. When the
UVLO pin is low, the outputs and the VCC regulator are
disabled, and the LM5032 enters a low power mode. If VCC
pin is not powered from an external source, the current into
VIN drops to a nominal 500 µA. If the VCC pin is powered
from an external source, the current into VIN is nominally 50
µA, and the current into the VCC pin is approximately 4.3
mA. To disable one regulator without affecting the other, see
the description of the Soft-start section.
Startup Regulator, VIN, VCC
The high voltage startup regulator is integral to the LM5032.
The input pin VIN can be connected directly to a voltage
between 13V and 100V, with transient capability to 105V.
The startup regulator provides bias voltages to the series
pass VCC regulator and the UVLO circuit. The VCC regulator
is disabled until the voltage at the UVLO pin (described
above) exceeds 1.25V. For applications where VPWR ex-
ceeds 100V the internal startup regulator can be powered
from an external startup regulator or other available low
voltage source. See the Applications Information section for
details.
The VCC under-voltage threshold circuit (UVT) monitors the
VCC regulator output. When the series pass regulator is
enabled and the internal VCC voltage increases to > 7.6V,
the UVT comparator activates the PWM controller and out-
put drivers via the Drivers Off signal. The UVT comparator
has built-in hysteresis, with the lower threshold nominally set
to 6.2V. See Figure 2 and Figure 15.
When enabled, the VCC regulated output is 7.7V ±4% with
current limited to a minimum of 19 mA (typically 22 mA). The
regulator’s output impedance is ) 6Ω.
The VCC pin requires a capacitor to ground for stability, as
well as to provide the surge currents to the external MOS-
FETs via the gate driver outputs. The capacitor should be
physically close to the VCC and GND pins.
In most applications it is necessary to power VCC from an
external source as the average current required at the output
drivers may exceed the current capability of the internal
regulator and/or the thermal capability of the LM5032 pack-
age (see Figure 5). Normally the external source is derived
from the converter’s power stage once the LM5032 outputs
are active. Refer to the Applications Information section for
more information.
Drivers Off, VCC Disable
Referring to Figure 15, Drivers Off and VCC Disable are
internal signals which, when active disable portions of the
LM5032. If the UVLO pin is below 1.25V, or if the thermal
shutdown activates, the VCC Disable line switches high to
disable the VCC regulator. UVLO also activates the Drivers
Off signal to disable the output drivers, connect the SS1,
SS2, COMP1, COMP2 and RES pins to ground, and enable
the 50 µA Soft-start current sources.
If the VCC voltage falls below the under-voltage threshold of
6.2V , the UVT comparator activates only the Drivers Off
signal. The output drivers are disabled but the VCC regulator
is not disabled. Additionally, the CS1, CS2, SS1, SS2,
COMP1, COMP2 and RES pins are internally grounded, and
the 50 µA Soft-start current sources are enabled.
Oscillator
The oscillator frequency is set with an external resistor RT
connected between the RT/SYNC and GND1 pins. The re-
sistor value is calculated from:
20135020
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FIGURE 15. Drivers Off and VCC Disable
(1)
where FS is the desired oscillator frequency in kHz (maxi-
mum of 2 MHz), and RT is in kΩ. See Figure 8. The two gate
driver outputs (OUT1 and OUT2) switch at half the oscillator
frequency and 180˚ out of phase with each other. The volt-
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| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet LM5032.PDF ] | |
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