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PDF EM6125 Data sheet ( Hoja de datos )
| Número de pieza | EM6125 | |
| Descripción | Digitally programmable 65 and 81 multiplex rate LCD Controller and Driver | |
| Fabricantes | EM Microelectronic | |
| Logotipo |  |
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EM MICROELECTRONIC - MARIN SA
EM6125
Digitally programmable 65 and 81 multiplex rate LCD
Controller and Driver
Features
Slim IC for COG, COF and COB technologies
I2C & Serial bus interface
Internal display data RAM
2 digitally programmable multiplex rates :
- 81 rows x 102 columns
- 65 rows x 118 columns
LCD supply voltage internally generated and digitally
programmable from 3V to 11V
Low operating current consumption: 120µA (typ)
No external components needed except one VLCD
capacitor
On chip
- 4 intermediate bias voltages generation
- Oscillator for LCD refresh (no external components
required)
High noise immunity on inputs
Row and column drivers mirroring for COG or COF
connections flexibility
Partial display mode with 17 active rows for current
consumption reduction
Sleep mode for a nearly null current consumption
Wide VDD supply voltage from 1.8V to 5V.
Wide temperature range: -40°C to +85°C
Description
The EM6125 is a bit map controller and driver for full dot
matrix monochrome STN LCD displays. The driving
capability is 81 rows x 102 columns (10 rows of
characters + one row of icons) or 65 rows x 118 columns
(8 rows of characters + one row of icons). There is a one
to one relation between LCD pixels and bits of the
Display Data RAM.
The EM6125 is extremely low power consumption LCD
controller and driver product. The typical current
consumption is about 120µA with no external component
except the capacitor connected to VLCD. One important
feature on EM6125 is the partial display mode, which
enables important current consumption reduction. With
this function selected, only 17 rows remain active,
needed VLCD decreases and the commutation
frequencies of row and column drivers are also
decreased. These three effects of partial display mode
reduce drastically current consumption.
Typical Applications
Mobile phones
Smart cards
Automotive displays
Portable, battery operated products
Balances and scales, utility meters
Typical Operating Configuration
41 row drivers
40 row drivers
102 columns outputs
EM6125
VLCD SCL SDA RES Vss1 Vss2 VDD1 VDD2 VHV
Pin Configuration
Figure 1
Copyright 2001, EM Microelectronic-Marin SA
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Figure 2
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EM6125
5 Timing Characteristics
VSS1,2 = 0V, VDD1 = VDD2 = 1.8V, VHV = 2.4V, TA = -40°C to +85 °C unless otherwise specified.
Parameter
Internal frame frequency
for LCD refresh
Minimum reset pulse width
I2C timing characteristics
SCL frequency
SCL low period
SCL high period
SDA setup time
SDA hold time
SCL and SDA rise time
SCL and SDA fall time
Setup time for a repeated
start condition
Hold time for a
start condition
Setup time for a
stop condition
Spike width on SCL and SDA
Symbol
fFR
tRW
fI2C
tLOW
tHIGH
tSUDAT
tHDDAT
tR
tF
tSUSTA
tHDSTA
tSUSTO
tSW
Test conditions
(note 1)
Min.
70
Typ.
75 x
mux
350
100
10
20
20
20
20
Time before a new transmission can start
Capacitive bus line load
Serial bus timing characteristics
SCL frequency
SCL low period
SCL high period
SDA setup time
SDA hold time
SCL rise time
SCL fall time
CS setup time
CS hold time
Time before a new transmission can
start, CS minimum high time.
tBUF
Cb
fSER
tCL
tCH
tDS
tDH
tCR
tCF
tSUCS
tHDCS
tBUFCS
100
70
130
20
50
10
130
70
Note 1: Measured on pad FR.
Max. Units
Hz
ns
1600
200
200
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
20 ns
ns
400 pF
4 MHz
ns
ns
ns
ns
200 ns
200 ns
ns
ns
ns
Copyright 2001, EM Microelectronic-Marin SA
5
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EM6125
8 Functional description
8.1 Selection of interface type
There are two different serial interfaces available on EM6125. Selection depends on logical value applied on pad I.
If I = 0, serial interface is selected: 3 wires with Chip Select CS, Serial Clock SCL and Serial Data SDA.
If I = 1, I2C protocol is selected: 2 wires with Serial Clock SCL and Serial Data SDA. CS must be connected to VSS
or VDD1.
I Interface
0 3 wires serial interface
1 I2C
Table 2: Interface selection
8.2 Serial interface
The serial interface consists of 3 wires: Chip Select CS, Serial Clock SCL and Serial Data SDA. The information is
exchanged byte-wide and is shifted serially in the LCD driver at SCL fall edge.
SDA
SCL
Data sampled on SCL fall edge
Data stable, data valid Change of data allowed
Figure 10: Serial interface, 1 bit transfer
Transfer of data is unidirectional from micro controller to EM6125. When CS is activated at low level the communication is
enabled and must stay low for the rest of the transaction. Data transfer begins with one control byte. This control bytes is
transferred MSB first, it consists in:
MSB
LSB
C0 DC Test[2] Test[1] Test[0] Ini[2] Ini[1] Ini[0]
C0 is the continuation bit:
If C0 = 1, the control byte is followed by 1 data byte only, the next byte is a new control byte.
If C0 = 0, all the following bytes are data bytes until data transfer is stopped.
DC selects data bytes or command bytes to be send after the control byte:
If DC = 1, the following data byte(s) is (are) written in the Display Data RAM. First data byte is stored at the
address specified by the x-address and y-address pointers. Data pointers are automatically updated for each byte
written in the DDRAM (see DDRAM description).
IF DC = 0, the following data byte is a command byte. It enables initialization of functions (multiplex rate, number
of voltage multiplier stages, VLCD programming, partial display settings…).
Bits ini2, ini1 and ini0 select the initialization register to be set by the following command byte (see Table 4: EM6125
instructions).
Copyright 2001, EM Microelectronic-Marin SA
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EM6125.PDF ] | |
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