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PDF TMP90C846 Data sheet ( Hoja de datos )
| Número de pieza | TMP90C846 | |
| Descripción | CMOS 8-Bit Microcontrollers | |
| Fabricantes | Toshiba | |
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TOSHIBA
TLCS-90 Series
TMP90C846
CMOS 8–Bit Microcontroller
TMP90C846F
1. Outline and Characteristics
The TMP90C846 is an advanced 8-bit microcontroller
(4) Built-in RAM: 256 bytes
developed for application in the control of HDD/FDD high-
(5) Memory expansion capability
speed mechanisms. The built-in functions include a high-speed
External program memory: 56K bytes
A/D converter (minimum sampling rate: 400ns @ 10MHz)
with an external start function, and a D/A converter.
The TMP90C846, integrates 8-bit CPU, ROM, RAM,
high-speed A/D converter, D/A converter, and multi-function
mtimer/event counter in a single-chip.
oThe TMP90C846 uses a 44-pin mini flat package (QFP44-P-
1414D).
.cThe following are the features of the TMP90C846:
(1) Highly efficient instruction set:
U163 basic instructions
Division and multiplication instructions, 16-bit operation
t4instruction and bit manipulation operation instructions
and bit operation instructions.
e(2) Minimum instruction executing time: 400ns (@ 10MHz)
e(3) Built-in ROM: 8K bytes
External data memory: 56K bytes
(6) Highly-speed A/D converter (2 channels)
• Minimum sampling rate: 400ns (@ 10MHz)
• 16-byte FIFO RAM (conversion data storage)
• External start, software start (one-time conversion,
repeat conversion
(7) 8-bit voltage output type D/A converter (2 channels)
(8) Multi-function 16-bit timer/event counter (1 channel)
(9) 8-bit timer (4 channels)
(10) Interrupt function: 9 internal, 4 external
(11) Micro DMA function (10 channels)
(12) Watchdog timer function
(13) Zero cross detector (2 pins)
(14) I/O ports (28 pins)
(15) Standby function (4 HALT modes)
www.DataSh taSheet4U.comThe information contained here is subject to change without notice.
aThe information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
.Dequipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-
ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
wof safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
wwTOSHIBA CORPORATION
1/98
1 page  
TMP90C846
3. Operation
This section explains the functions and basic operations of the
TMP90C846.
3.1 CPU
The TMP90C846 has a built-in high-performance 8-bit CPU.
Refer to the book TLCS-90 Series CPU Core Architecture con-
cerning the CPU operation.
Following section explains the CPU functions unique to
the TMP90C846 that are not explained in that book.
3.1.1 Resets
The basic reset timing is shown in Figure 3.1.
To reset the TMP90C846, it is necessary to maintain the
RESET input at “0” for at least 10 system clocks (10 states:
2µsec @ 10MHz) with the power supply voltage within the
operating range and with stabilized oscillation.
When a reset is received, I/O port 0 (address data bus
AD0 ~ AD7), port 1 (address bus A8 ~ A15), and port 2 are all
set to input status (high impedance). Output ports P32 (RD)
and P33 (WR) and CLK are all set to “1”. ALE is cleared to
“0”.The registers of the CPU also remain unchanged. Note,
however, that the program counter PC, the interrupt enable flag
IFF are cleared to “0”. Register A shows an reset, because WR is
set to “1” before undefined address/data is outputted.
When the reset is released, instruction execution starts
from address 0000H.
TOSHIBA CORPORATION
5/98
5 Page 
TMP90C846
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
Table 3.3 (1) Interrupt Sources
Type Interrupt request source
Non-
maskable
Maskable
SWI instruction
NMI (NMI pin input (programmable))
INT WD (watchdog)
INTO (External input 0)
INTTO (Timer 0)
INTT1 (Timer 1)
INTAD (A/D converter)
INTT2 (Timer 2)
INTT3 (Timer 3)
INTT4 (Timer 4)
INT1 (External input 1)
INTT5 (Timer 5)
INT2 (External input 2)
Vector
Value
÷8
–
–
–
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
Vector
Value
10H
18H
20H
28H
30H
38H
40H
48H
50H
58H
60H
68H
70H
General-
purpose interrupt
processing
start address
0010H
0018H
0020H
0028H
0030H
0030H
0040H
0048H
0050H
0058H
0060H
0068H
0070H
Micro DMA
processing
parameter
start address
–
–
–
FF28H
FF30H
FF38H
FF40H
FF48H
FF50H
FF58H
FF60H
FF68H
FF70H
The “priority” used in Table 3.3 (1) indicates the priority in
which interrupt sources are received by the CPU when multiple
interrupt requests are generated simultaneously.
For example, if the interrupt requests with the priority 4
and 5 are generated simultaneously, the CPU will receive the
interrupt request with the priority 4 first. When the priority 4
interrupt processing is ended with the RETI instruction, the
CPU will receive the interrupt with the priority 5. If the interrupt
processing program with the priority 4 is interrupted by execting
th EI instuction, the CPU will receive the priority 5 interrupt
request.
When multiple interrupt request are generated simultaneously,
the built-in interrupt controller only determines the priority of
the interrupt sources received by the CPU. There is no function
for comparing the priority between the currently processed
interrupt and the currently request interrupt.
Another interrupt can be enabled while an interrupt is
processed by setting the interrupt enable flag IFF to enable.
TOSHIBA CORPORATION
11/98
11 Page | ||
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| PDF Descargar | [ Datasheet TMP90C846.PDF ] | |
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