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PDF MPC9449 Data sheet ( Hoja de datos )
| Número de pieza | MPC9449 | |
| Descripción | 3.3V / 2.5 V 1:15 PECL/LVCMOS | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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1. MPC9449  Hay una vista previa y un enlace de descarga de MPC9449 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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MOTOROLA
Freescale Semiconductor, Inc.
Order Number: MPC9449/D
SEMICONDUCTOR TECHNICAL DATA
Rev 1, 08/2002
3.3V/2.5V 1:15 PECL/LVCMOS
Clock Fanout Buffer
MPC9449
The MPC9449 is a 3.3V or 2.5V compatible, 1:15 clock fanout buffer
targeted for high performance clock tree applications. With output
frequencies up to 200 MHz and output skews less than 200 ps the device
meets the needs of the most demanding clock applications.
Features
• 15 LVCMOS compatible clock outputs
3.3V/2.5V 1:15
PECL/LVCMOS
• Two selectable LVCMOS and one differential LVPECL compatible clock
inputs
CLOCK FANOUT BUFFER
• Selectable output frequency divider (divide-by-one and divide-by-two)
• Maximum clock frequency of 200 MHz
• Maximum clock skew of 200 ps
• High-impedance output control
• 3.3V or 2.5V power supply
• Drives up to 30 series terminated clock lines
• Ambient temperature range –40°C to +85°C
• 52 lead LQFP packaging
• Supports clock distribution in networking, telecommunication and
computing applications
• Pin and function compatible to MPC949
FA SUFFIX
52 LEAD LQFP PACKAGE
CASE 848D
Functional Description
The MPC9449 is specifically designed to distribute LVCMOS
compatible clock signals up to a frequency of 200 MHz. The device has
15 identical outputs, organized in 4 output banks. Each output bank
provides a retimed or frequency divided copy of the input signal with a
near zero skew. The output buffer supports driving of 50Ω terminated
transmission lines on the incident edge: each output is capable of driving
either one parallel terminated or two series terminated transmission lines.
Two selectable LVCMOS compatible clock inputs are available. This feature supports redundant differential clock sources. In
addition, the MPC9449 accepts one differential PECL clock signal. The DSELx pins choose between division of the input
reference frequency by one or two. The frequency divider can be set individually for each of the four output banks. Applying the
OE control will force the outputs into high-impedance mode.
All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a
2.5V or 3.3V power supply and an ambient temperature range of –40°C to +85°C. The MPC9449 is pin and function compatible
but performance-enhanced to the MPC949. The device is packaged in a 52-lead LQFP package.
© Motorola, Inc. 2002
For More Information On This Product,
1 Go to: www.freescale.com
1 page  
Freescale Semiconductor, Inc.
MPC9449
Table 7: DC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40°C to 85°C)
Symbol
Characteristics
Min
Typ
Max Unit
Condition
VIH Input high voltage
VIL Input low voltage
1.7 VCC + 0.3 V LVCMOS
-0.3 0.7 V LVCMOS
VPP
Peak-to-peak input voltage
PCLK, PCLK
250
mV LVPECL
VCMRa
VOH
Common Mode Range
Output High Voltage
PCLK, PCLK
1.0
1.8
VCC-0.6
V LVPECL
V IOH=-15 mAb
VOL
ZOUT
IIN
Output Low Voltage
Output impedance
Input Currentc
17 - 20
0.6
±200
V IOL= 15 mA
W
µA VIN=VCC or GND
ICC Maximum Quiescent Supply Current
10 mA All VCC Pins
a VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
b The MPC9449 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT.
c Inputs have pull-down or pull-up resistors affecting the input current.
Table 8: AC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40°C to 85°C)a
Symbol
Characteristics
Min Typ
Max Unit Condition
VPP
Peak-to-peak input voltage
PCLK, PCLK
400
1000
mV LVPECL
VCMRb
fmax
fref
tP, REF
tr, tf
tsk(O)
Common Mode Range
Output frequency
Input Frequency
Reference Input Pulse Width
CCLK Input Rise/Fall Time
Output-to-output Skew
same frequency
different frequencies
PCLK, PCLK
Qa outputs
Qb outputs
Qc outputs
Qd outputs
All outputs
All outputs
1.2
0
0
1.5
VCC-0.6
200
200
1.0
50
50
50
100
200
300
V
MHz
MHz
ns
ns
ps
ps
ps
ps
ps
ps
LVPECL
0.7 to 1.7V
tsk(PP) Device-to-device Skew
5.0 ns
tSK(P)
Output Pulse Skew
350 ps DCREF = 50%
tPLH, HL Propagation delay
CCLK0 or CCLK1 to any Q
1.0
3.5
7.0 ns
PCLK to any Q
1.0
3.5
7.0 ns
tPLZ, HZ Output Disable Time
OE to any Q
11 ns
tPZL, LZ
tr, tf
Output Enable Time
Output Rise/Fall Timec
OE to any Q
0.1
11 ns
1.0 ns 0.6 to 1.8V
tJIT(CC) Cycle-to-cycle jitter
RMS (1 σ)
TBD
ps
a AC characteristics apply for parallel output termination of 50Ω to VTT.
b VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts propagation delay.
c An input rise/fall time greater than that specified may be used, but AC characteristics are not guaranteed under such a condition.
For MorGeoIntfoo:rwmwa5twio.fnreOenscTahlies.cPoromduct,
MOTOROLA
5 Page 
Freescale Semiconductor, Inc.
NOTES
MPC9449
For MorGeoIntfoo:rwmwa1t1wio.fnreOenscTahlies.cPoromduct,
MOTOROLA
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MPC9449.PDF ] | |
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