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PDF MC54HC165 Data sheet ( Hoja de datos )

Número de pieza MC54HC165
Descripción 8-Bit Serial or Parallel-Input/Serial-Output Shift Register
Fabricantes Motorola Semiconductors 
Logotipo Motorola Semiconductors Logotipo



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No Preview Available ! MC54HC165 Hoja de datos, Descripción, Manual

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High–Performance Silicon–Gate CMOS
The MC54/74HC165 is identical in pinout to the LS165. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is an 8–bit shift register with complementary outputs from the
last stage. Data may be loaded into the register either in parallel or in serial
form. When the Serial Shift/Parallel Load input is low, the data is loaded
asynchronously in parallel. When the Serial Shift/Parallel Load input is high,
the data is loaded serially on the rising edge of either Clock or Clock Inhibit
(see the Function Table).
The 2–input NOR clock may be used either by combining two independent
clock sources or by designating one of the clock inputs to act as a clock
inhibit.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 286 FETs or 71.5 Equivalent Gates
LOGIC DIAGRAM
PARALLEL
DATA
INPUTS
A 11
B 12
C 13
D 14
E3
F4
G5
SERIAL
DATA
INPUT
H6
SA 10
SERIAL SHIFT/PARALLEL LOAD 1
9 QH
7
QH
SERIAL
DATA
OUTPUTS
PIN 16 = VCC
PIN 8 = GND
MC54/74HC165
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
SERIAL SHIFT/
PARALLEL LOAD
1
CLOCK 2
16 VCC
15 CLOCK INHIBIT
E3
14 D
F4
13 C
G5
12 B
H6
11 A
QH 7
GND 8
10 SA
9 QH
CLOCK 2
CLOCK INHIBIT 15
FUNCTION TABLE
Serial Shift/
Parallel Load
L
Inputs
Clock
Clock Inhibit
XX
SA
X
Internal Stages Output
A – H QA QB QH
Operation
ah
a
b
h Asynchronous Parallel Load
H
H
L
L
L
H
X
X
L
H
QAn
QAn
QGn
QGn
Serial Shift via Clock
HL
HL
L
H
X
X
L
H
QAn
QAn
QGn
QGn
Serial Shift via Clock Inhibit
H XHXX
H HXXX
No Change
Inhibited Clock
H L LXX
No Change
No Clock
X = don’t care
QAn – QGn = Data shifted from the preceding stage
10/95
© Motorola, Inc. 1995
1 REV 6

1 page




MC54HC165 pdf
MC54/74HC165
SWITCHING WAVEFORMS
CLOCK
OR CLOCK INHIBIT
tr
90%
50%
10%
tw
tf
QH OR QH
90%
50%
10%
1/fmax
tPLH tPHL
tTLH tTHL
VCC
GND tw
SERIAL SHIFT/
50%
PARALLEL LOAD
tPLH
QH OR QH
50%
50%
tPHL
VCC
GND
Figure 1. Serial–Shift Mode
Figure 2. Parallel–Load Mode
tr
INPUT H
tPLH
QH OR QH
90%
50%
10%
90%
50%
10%
tTLH
tf
VCC
GND
tPHL
tTHL
Figure 3. Parallel–Load Mode
INPUTS A–H
VALID
50%
VCC
GND
SERIAL SHIFT/
PARALLEL LOAD
tsu th
VCC
GND
ASYNCHRONOUS PARALLEL
LOAD
(LEVEL SENSITIVE)
Figure 4. Parallel–Load Mode
INPUT SA
CLOCK
OR CLOCK INHIBIT
VALID
50%
tsu th
50%
SERIAL SHIFT/
VCC PARALLEL LOAD
GND
CLOCK
VCC OR CLOCK INHIBIT
GND
50%
tsu th
50%
VCC
GND
VCC
GND
Figure 5. Serial–Shift Mode
Figure 6. Serial–Shift Mode
CLOCK INHIBIT
CLOCK 2 INHIBITED
50%
VCC
GND
CLOCK
tsu trec
50%
VCC
GND
Figure 7. Serial–Shift, Clock–Inhibit Mode
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 8. Test Circuit
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA

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