PDF HY57V561620T Data sheet ( Hoja de datos )

Número de pieza	HY57V561620T
Descripción	4Banks x 4M x 16Bit Synchronous DRAM
Fabricantes	Hynix Semiconductor
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No Preview Available ! HY57V561620(L)T 4Banks x 4M x 16Bit Synchronous DRAM DESCRIPTION The HY57V561620T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of 4,194,304x16. The HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline ( CAS latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • Single 3.3V ± 0.3V power supply • Auto refresh and self refresh • All device pins are compatible with LVTTL interface • 8192 refresh cycles / 64ms • JEDEC standard 400mil 54pin TSOP-II with 0.8mm • Programmable Burst Length and Burst Type of pin pitch - 1, 2, 4, 8 and Full Page for Sequential Burst • All inputs and outputs referenced to positive edge of system clock - 1, 2, 4 and 8 for Interleave Burst • Data mask function by UDQM and LDQM • Programmable CAS Latency ; 2, 3 Clocks • Internal four banks operation ORDERING INFORMATION Part No. HY57V561620T-HP HY57V561620T-H HY57V561620T-8 HY57V561620T-P HY57V561620T-S HY57V561620LT-HP HY57V561620LT-H HY57V561620LT-8 HY57V561620LT-P HY57V561620LT-S Clock Frequency 133MHz 133MHz 125MHz 100MHz 100MHz 133MHz 133MHz 125MHz 100MHz 100MHz Power Normal Lower Power Organization Interface Package 4Banks x 4Mbits x16 LVTTL 400mil 54pin TSOP II This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Revision 1.8 / Apr.01 1 page HY57V561620(L)T CAPACITANCE (TA=25°C, f=1MHz) Parameter Pin Symbol Input capacitance Data input / output capacitance CLK A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE, UDQM, LDQM DQ0 ~ DQ15 CI1 CI2 CI/O -H Min Max 2.5 3.5 2.5 3.8 4.0 6.5 -8/P/S Min Max 2.5 4.0 2.5 5.0 4.0 6.5 Unit pF pF pF OUTPUT LOAD CIRCUIT Output Vtt=1.4V RT=250 Ω Output 50pF 50pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V) Parameter Input leakage current Output leakage current Output high voltage Output low voltage Symbol ILI ILO VOH VOL Min. -1 -1 2.4 - Note : 1. VIN = 0 to 3.6V, All other pins are not under test = 0V 2. DOUT is disabled, VOUT=0 to 3.6V Max 1 1 - 0.4 Unit uA uA V V Note 1 2 IOH = -4mA IOL =+4mA Revision 1.8 / Apr.01 5 Page DEVICE OPERATING OPTION TABLE HY57V561620(L)T-HP 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) CAS Latency 3CLKs 3CLKs 2CLKs HY57V561620(L)T-H tRCD 3CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) CAS Latency 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 6CLKs 6CLKs 6CLKs HY57V561620(L)T-8 125MHz(8ns) 100MHz(10ns) 83MHz(12ns) CAS Latency 3CLKs 3CLKs 2CLKs HY57V561620(L)T-P tRCD 3CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 4CLKs 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) CAS Latency 2CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs HY57V561620(L)T-S 100MHz(10.0ns) 83MHz(12.0ns) 66MHz(15.0ns) CAS Latency 3CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs tRC 9CLKs 9CLKs 7CLKs tRC 9CLKs 9CLKs 9CLKs tRC 9CLKs 9CLKs 6CLKs tRC 7CLKs 7CLKs 6CLKs tRC 7CLKs 7CLKs 6CLKs tRP 3CLKs 3CLKs 2CLKs tRP 3CLKs 3CLKs 3CLKs tRP 3CLKs 3CLKs 2CLKs tRP 2CLKs 2CLKs 2CLKs tRP 2CLKs 2CLKs 2CLKs HY57V561620(L)T tAC 5.4ns 6ns 6ns tOH 2.7ns 3ns 3ns tAC 5.4ns 6ns 6ns tOH 2.7ns 3ns 3ns tAC tOH 6ns 3ns 6ns 3ns 6ns 3ns tAC tOH 6ns 3ns 6ns 3ns 6ns 3ns tAC tOH 6ns 3ns 6ns 3ns 6ns 3ns Revision 1.8 / Apr.01 11 Page

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