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PDF LMX2323 Data sheet ( Hoja de datos )
| Número de pieza | LMX2323 | |
| Descripción | PLLatinum? 2.0 GHz Frequency Synthesizer for RF Personal Communications | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LMX2323 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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October 2000
LMX2323
PLLatinum™ 2.0 GHz Frequency Synthesizer for RF
Personal Communications
General Description
The LMX2323 is a high performance frequency synthesizer
with integrated 32/33 dual modulus prescaler designed for
RF operation up to 2.0 GHz. Using a proprietary digital
phase locked loop technique, the LMX2323’s linear phase
detector characteristics can generate very stable, low noise
control signals for UHF and VHF voltage controlled oscilla-
tors.
Serial data is transferred into the LMX2323 via a three-line
MICROWIRE™ interface (Data, LE, Clock). Supply voltage
range is from 2.7V to 5.5V. The LMX2323 features very low
curent consumption, typically 3.5mA at 3V. The charge pump
provides 4 mA output current.
The LMX2323 is manufactured using National’s ABiC V
BiCMOS process and is packaged in a 16-pin TSSOP.
Features
n RF operation up to 2.0 GHz
n 2.7V to 5.5V operation
n Low current consumption: Icc = 3.5mA (typ) at
Vcc=3.0V
n Digital Lock Detect
n Dual modulus prescaler: 32/33
n Internal balanced, low leakage charge pump
Applications
n Cellular telephone systems (GSM, NADC, CDMA, PDC,
PHS)
n Personal wireless communications (DCS-1800, DECT,
CT-1+)
n Wireless local area networks (WLANs)
n DCS/PCS infrastructure equipment
n Other wireless communication systems
Functional Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
MICROWIRE™ and PLLatinum™ are trademarks of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS101362
DS101362-1
www.national.com
1 page  
Typical Performance Characteristics
ICCvs VCC
Charge Pump Current vs VCPo Output
DS101362-13
RF Input Sensitivity vs Frequency
DS101362-14
Oscillator Input Sensitivity
DS101362-15
DS101362-16
5 www.national.com
5 Page 
2.0 Programming Description (Continued)
2. Both synchronous and asynchronous power down modes are available with the LMX2323 to be able to adapt to different
types of applications. The MICROWIRE control register remains active and capable of loading and latching in data during all
of the powerdown modes.
Synchronous Power down Mode
The PLL loops can be synchronously powered down by setting the counter reset mode bit to LOW (N[2] = 0) and its power down
mode bit to HIGH (N[1] = 1). The power down function is gated by the charge pump. Once the power down mode and counter
reset mode bits are loaded, the part will go into power down mode upon the completion of a charge pump pulse event.
Asynchronous Power down Mode
The PLL loops can be asynchronously powered down by setting the counter reset mode bit to HIGH (N[2] = 1) and its power down
mode bit to HIGH (N[1] = 1). The power down function is NOT gated by the charge pump. Once the power down and counter reset
mode bits are loaded, the part will go into power down mode immediately.
The R and N counters are disabled and held at load point during the synchronous and asynchronous power down modes. This
will allow a smooth acquisition of the RF signal when the PLL is programmed to power up. Upon powering up, both R and N
counters will start at the ‘zero’ state, and the relationship between R and N will not be random.
Serial Data Input Timing
DS101362-6
Notes: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6 V/ns with
amplitudes of 2.2V @ VCC = 2.7V and 2.6V @ VCC = 5.5V.
Phase Comparator and Internal Charge Pump Characteristics
Notes: Phase difference detection range: −2π to +2π
The minimum width pump up and pump down current pulses occur at the CPo pin when the loop is locked. PD_POL = 1
fr: Phase comparator input from the R divider
fp: Phase comparator input from the N divider
CPo: Charge pump output
DS101362-7
11 www.national.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LMX2323.PDF ] | |
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