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PDF LT1947 Data sheet ( Hoja de datos )
| Número de pieza | LT1947 | |
| Descripción | Adjustable Output TFT-LCD Triple Switching Regulator | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LT1947
Adjustable Output TFT-LCD
Triple Switching Regulator
FEATURES
s Complete Solution Under 1.2mm
s Develops Three Outputs from a 3.3V or 5V Supply
s Externally Programmable VON Delay
s Fixed Frequency Low Noise Outputs
s All Ceramic Capacitors
s 3MHz Switching Frequency
s Fast Transient Response
s Few External Components Required
s 2.7V to 8V Input Range
s Adjustable AVDD and VON Voltages
s Tiny 10-Lead MSOP Package
U
APPLICATIO S
s TFT-LCD Notebook Display Panels
s TFT-LCD Desktop Monitor Display Panels
s Digital Cameras
s Handheld Computers
DESCRIPTIO
The LT®1947 is a highly integrated multiple output DC/DC
converter designed for use in TFT-LCD panels. The device
contains two independent switching regulators. The main
regulator has an adjustable output voltage with an internal
1.1A switch that can generate a boosted voltage as high as
30V. The second regulator’s output is also adjustable up
to 30V and can deliver 10mA for positive bias. A simple
level-shift charge pump off the main switch node gener-
ates the negative bias voltage. An external capacitor sets
the delay time from AVDD’s final value to the rising edge at
the VON pin. The 3MHz switching frequency allows the use
of tiny low profile chip inductors and capacitors through-
out, providing a low noise, low cost total solution with all
components under 1.2mm in height. The device operates
from an input range of 2.7V to 8V and is available in a
10-lead MSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
VIN
C1
2.2µF
CERAMIC
SHUTDOWN
D3 D4
L1
3.3µH
C6
0.68µF
L2
4.7µH
VIN
SW2
SW1
FB1
D1
D2
C3
220nF
R3
182k
R4
10k
VO2 LT1947
FB2 VON
SHDN CT GND
C5
10nF
R1
53.6k
R2
10k
VOFF
–8V
C4 10mA
0.68µF
CERAMIC
AVDD
8V
200mA
C2
3.3µF
CERAMIC
×2
VON
24V
10mA
C1: TAIYO YUDEN LMK316BJ225MD
C2: TAIYO YUDEN LMK325BJ335MD ×2
C3: AVX 0.22µF 25V X7R
C4, C6: TAIYO YUDEN LMK107BJ684MA
D1: MBRM120LT3
D2: CMDSH-3
1947 F01
D3, D4: BAT54S DUAL DIODE
L1: SUMIDA CLQ4D103R3
L2: TAIYO YUDEN LB2012B4R7M
Figure 1. 3.3V Powered TFT-LCD Bias Generator
VSHDN
5V/DIV
VON
20V/DIV
AVDD
10V/DIV
VOFF
10V/DIV
Start-Up Waveforms
2ms/DIV
1947 TA01.tif
1947f
1
1 page  
U
OPERATIO
To best understand operation of the LT1947, please refer
to the LT1947 Block Diagram. The device contains two
switching regulators, a timer and a high side switch. Three
outputs can be generated: an adjustable AVDD output, a
charge-pumped inversion of the AVDD output called VOFF,
and a time delayed adjustable output called VON. Q3 keeps
VON off for an externally set time interval, set by a capacitor
connected to the CT pin.
The switching frequency of both switchers is 3MHz, set
internally. The switchers are current mode and are inter-
nally compensated. The main AVDD switcher is current
limited at 1.1A, while the second VON switcher is limited to
350mA. They share the same 1.26V reference voltage.
When the input voltage is below approximately 2.7V, an
undervoltage lockout circuit disables switching.
When AVDD is less than its final voltage, Q4 is turned on,
holding the CT pin at ground. When AVDD reaches final
value, Q4 lets go of the CT pin, allowing the 5.5µA current
source to charge the external capacitor, CT. When the
voltage on the CT pin reaches 1.28V, Q3 turns on,
LT1947
connecting VO2 to VON. Capacitor value can be calculated
using the following formula:
C = (5.5µA • tDELAY)/1.28V
A 10nF capacitor results in approximately 2.3ms of delay.
Layout Hints
The high speed operation of the LT1947 mandates careful
attention to layout for proper performance. Be sure to keep
input capacitor C1 as close as possible to the IC and
minimize trace area and length at the SW and FB pins.
Always use a ground plane under the switching regulator
to minimize interplane coupling. Figure 2 shows the rec-
ommended component placement.
Soft-Start
For applications requiring soft-start, a circuit consisting of
RSS and CSS tied to the SHDN pin can be used, as shown
in Figure 3. For a combination of 33.2k/33nF, AVDD rises
to its final value in approximately 3ms.
R3
GND R4
R1 R2
C5
L1
VIN
1
2
3
4
5
C6
LT1947
10
9
8
7
6
C1
L2
C3 VIN
VON
D2
D1
AVDD
D3 D4
C4
C2
GND
SHDN
VOFF
Figure 2. Recommended Component Placement
1947 F02
1947f
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet LT1947.PDF ] | |
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